^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu-sun8i-a83t.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCU_SUN8I_A83T_LOCK_REG 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * P should only be used for output frequencies lower than 228 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * For now we can just model it as a multiplier clock, and force P to /1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN8I_A83T_PLL_C0CPUX_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN8I_A83T_PLL_C1CPUX_REG 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct ccu_mult pll_c0cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .lock = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .reg = SUN8I_A83T_PLL_C0CPUX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct ccu_mult pll_c1cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .lock = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .reg = SUN8I_A83T_PLL_C1CPUX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The Audio PLL has d1, d2 dividers in addition to the usual N, M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * and 24.576 MHz, ignore them for now. Enforce the default for them,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * which is d1 = 0, d2 = 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUN8I_A83T_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* clock rates doubled for post divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct ccu_nm pll_audio_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .lock = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .m = _SUNXI_CCU_DIV(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x284, BIT(31)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg = SUN8I_A83T_PLL_AUDIO_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .features = CCU_FEATURE_LOCK_REG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CCU_FEATURE_FIXED_POSTDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CCU_FEATURE_SIGMA_DELTA_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &ccu_nm_ops, CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct ccu_nkmp pll_video0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .lock = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .p = _SUNXI_CCU_DIV(0, 2), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .max_rate = 3000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct ccu_nkmp pll_ve_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .lock = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct ccu_nkmp pll_ddr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .lock = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct ccu_nkmp pll_periph_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .lock = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct ccu_nkmp pll_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .lock = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reg = 0x038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct ccu_nkmp pll_hsic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .lock = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg = 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct ccu_nkmp pll_de_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .lock = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .reg = 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .hw.init = CLK_HW_INIT("pll-de", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct ccu_nkmp pll_video1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .lock = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .max_rate = 3000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg = 0x04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const ahb1_parents[] = { "osc16M-d512", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .index = 2, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char * const apb2_parents[] = { "osc16M-d512", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "pll-periph", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct ccu_mux_fixed_prediv ahb2_prediv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .index = 1, .div = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct ccu_mux ahb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .fixed_predivs = &ahb2_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .n_predivs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .reg = 0x05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .hw.init = CLK_HW_INIT_PARENTS("ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ahb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x060, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x064, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x064, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x064, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0x068, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x068, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x068, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const char * const cci400_parents[] = { "osc24M", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "pll-hsic" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct ccu_div cci400_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .reg = 0x078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .hw.init = CLK_HW_INIT_PARENTS("cci400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cci400_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0x088, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 0x088, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x08c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x08c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x090, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x090, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x090, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0x0cc, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct ccu_gate usb_hsic_12m_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .enable = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .reg = 0x0cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .prediv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .features = CCU_FEATURE_ALL_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .hw.init = CLK_HW_INIT("usb-hsic-12m", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &ccu_gate_ops, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* TODO divider has minimum of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const char * const tcon0_parents[] = { "pll-video0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const char * const tcon1_parents[] = { "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const u8 csi_mclk_table[] = { 0, 3, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) csi_mclk_parents, csi_mclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 8, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) BIT(15), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const char * const csi_sclk_parents[] = { "pll-periph", "pll-ve" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const u8 csi_sclk_table[] = { 0, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) csi_sclk_parents, csi_sclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 16, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 16, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const char * const hdmi_parents[] = { "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const char * const mbus_parents[] = { "osc24M", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const char * const mipi_dsi0_parents[] = { "pll-video0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const u8 mipi_dsi0_table[] = { 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mipi_dsi0_parents, mipi_dsi0_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const u8 mipi_dsi1_table[] = { 0, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mipi_dsi1_parents, mipi_dsi1_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x16c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const char * const gpu_memory_parents[] = { "pll-gpu", "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) gpu_memory_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x1a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct ccu_common *sun8i_a83t_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) &pll_c0cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) &pll_c1cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) &pll_audio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) &pll_periph_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &pll_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &c0cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &c1cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &axi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &axi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &bus_mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) &bus_ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) &bus_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &bus_tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &bus_tcon1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &bus_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &bus_tdm_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) &bus_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) &cci400_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) &ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &tdm_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &usb_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &usb_hsic_12m_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) &tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &tcon1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) &mipi_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &csi_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) &hdmi_slow_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) &mipi_dsi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &mipi_dsi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &gpu_core_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) &gpu_memory_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &gpu_hyd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct clk_hw_onecell_data sun8i_a83t_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [CLK_C0CPUX] = &c0cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [CLK_C1CPUX] = &c1cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [CLK_AXI0] = &axi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [CLK_AXI1] = &axi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [CLK_BUS_SS] = &bus_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [CLK_BUS_TDM] = &bus_tdm_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [CLK_CCI400] = &cci400_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [CLK_TDM] = &tdm_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [CLK_TCON0] = &tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [CLK_TCON1] = &tcon1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [RST_USB_HSIC] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [RST_DRAM] = { 0x0f4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [RST_BUS_SS] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [RST_BUS_NAND] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [RST_BUS_OTG] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [RST_BUS_TCON1] = { 0x2c4, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [RST_BUS_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [RST_BUS_TDM] = { 0x2d0, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [RST_BUS_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [RST_BUS_UART4] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct sunxi_ccu_desc sun8i_a83t_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .ccu_clks = sun8i_a83t_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .hw_clks = &sun8i_a83t_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .resets = sun8i_a83t_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .num_resets = ARRAY_SIZE(sun8i_a83t_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define SUN8I_A83T_PLL_P_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define SUN8I_A83T_PLL_N_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define SUN8I_A83T_PLL_N_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* bail out if P divider is not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * If P is used, output should be less than 288 MHz. When we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * set P to 1, we should also decrease the multiplier so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * output doesn't go out of range, but not too much such that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * the multiplier stays above 12, the minimal operation value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * To keep it simple, set the multiplier to 17, the reset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) SUN8I_A83T_PLL_N_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) val |= 17 << SUN8I_A83T_PLL_N_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* And clear P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int sun8i_a83t_ccu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Enforce d1 = 0, d2 = 1 for Audio PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) val &= ~BIT(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) val |= BIT(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Enforce P = 1 for both CPU cluster PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C0CPUX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C1CPUX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_a83t_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const struct of_device_id sun8i_a83t_ccu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { .compatible = "allwinner,sun8i-a83t-ccu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static struct platform_driver sun8i_a83t_ccu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .probe = sun8i_a83t_ccu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .name = "sun8i-a83t-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .of_match_table = sun8i_a83t_ccu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) builtin_platform_driver(sun8i_a83t_ccu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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