^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ccu-sun8i-a23-a33.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct ccu_nkmp pll_cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN8I_A33_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "osc24M", 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x284, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "osc24M", 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "osc24M", 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "osc24M", 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "osc24M", 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "osc24M", 0x038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * integer / fractional clock with switchable multipliers and dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This is not supported here. We hardcode the PLL to MIPI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SUN8I_A33_PLL_MIPI_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "pll-video", 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 8, 4, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) BIT(31) | BIT(23) | BIT(22), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "osc24M", 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "osc24M", 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct ccu_mult pll_ddr1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .reg = 0x04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char * const cpux_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "pll-cpux" , "pll-cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const char * const ahb1_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "axi" , "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct clk_div_table apb1_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x054, 8, 2, apb1_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const char * const apb2_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "pll-periph" , "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x064, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x064, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x064, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x064, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x064, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x068, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x088, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x088, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x08c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x08c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x090, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x090, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* TODO: the parent for most of the USB clocks is not known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x0cc, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0x0cc, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x0f4, 0, 4, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x0f8, 16, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x100, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0x100, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x100, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "pll-gpu", "pll-de" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const u8 de_table[] = { 0, 2, 3, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) de_parents, de_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x104, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) de_parents, de_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x10c, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "pll-mipi" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const u8 lcd_ch0_table[] = { 0, 2, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) lcd_ch0_parents, lcd_ch0_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x118, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const u8 lcd_ch1_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) lcd_ch1_parents, lcd_ch1_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x12c, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "pll-mipi", "pll-ve" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) csi_sclk_parents, csi_sclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 0x134, 16, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const u8 csi_mclk_table[] = { 0, 3, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) csi_mclk_parents, csi_mclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x134, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x140, BIT(30), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "pll-ddr0", "pll-ddr1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const u8 dsi_sclk_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dsi_sclk_parents, dsi_sclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0x168, 16, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const u8 dsi_dphy_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dsi_dphy_parents, dsi_dphy_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0x168, 0, 4, 8, 2, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) de_parents, de_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0x180, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const char * const ats_parents[] = { "osc24M", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0x1b0, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct ccu_common *sun8i_a33_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &pll_video_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &pll_periph_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &pll_mipi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &pll_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &pll_ddr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &bus_mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &bus_ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &bus_ehci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &bus_ohci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &bus_lcd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &bus_de_fe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &bus_de_be_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &bus_drc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &bus_sat_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) &bus_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &usb_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &usb_hsic_12M_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &usb_ohci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &dram_drc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) &dram_de_fe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) &dram_de_be_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) &de_be_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &de_fe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) &lcd_ch0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) &lcd_ch1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) &csi_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) &ac_dig_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &ac_dig_4x_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) &dsi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) &dsi_dphy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &drc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) &ats_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* We hardcode the divider to 1 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &pll_video_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) [CLK_CPUX] = &cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [CLK_BUS_SS] = &bus_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) [CLK_BUS_DRC] = &bus_drc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [CLK_BUS_SAT] = &bus_sat_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [CLK_DE_BE] = &de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [CLK_DE_FE] = &de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [CLK_AC_DIG] = &ac_dig_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [CLK_DRC] = &drc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [CLK_ATS] = &ats_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [RST_USB_HSIC] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [RST_BUS_SS] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [RST_BUS_NAND] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [RST_BUS_OTG] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [RST_BUS_LCD] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [RST_BUS_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [RST_BUS_DRC] = { 0x2c4, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [RST_BUS_SAT] = { 0x2c4, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [RST_BUS_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [RST_BUS_UART4] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .ccu_clks = sun8i_a33_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .num_ccu_clks = ARRAY_SIZE(sun8i_a33_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .hw_clks = &sun8i_a33_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .resets = sun8i_a33_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .common = &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* copy from pll_cpux_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static struct ccu_mux_nb sun8i_a33_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .common = &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .cm = &cpux_clk.mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .delay_us = 1, /* > 8 clock cycles at 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .bypass_index = 1, /* index of 24 MHz oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void __init sun8i_a33_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val &= ~GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Force PLL-MIPI to MIPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) val &= ~BIT(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Gate then ungate PLL CPU after any rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Reparent CPU during PLL CPU rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &sun8i_a33_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) sun8i_a33_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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