Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2016 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN6I_A31_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN6I_A31_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun6i-a31-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/sun6i-a31-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PLL_CPU		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_AUDIO_BASE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO_2X	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_4X	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_AUDIO_8X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_VIDEO0		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* The PLL_VIDEO0_2X clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_VE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_DDR		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* The PLL_PERIPH clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PLL_PERIPH_2X	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_PLL_VIDEO1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The PLL_VIDEO1_2X clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_PLL_GPU		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* The PLL_VIDEO1_2X clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_PLL9		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_PLL10		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* The CPUX clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_AXI			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_AHB1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_APB1		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_APB2		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* All the bus gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* The first bunch of module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* EMAC clock is not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_MDFS		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_SDRAM0		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_SDRAM1		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* All the DRAM gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Some more module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_MBUS0		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_MBUS1		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Some more module clocks and external clock outputs are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_NUMBER		(CLK_OUT_C + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* _CCU_SUN6I_A31_H_ */