^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on ccu-sun8i-h3.c by Maxime Ripard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "ccu_sdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "ccu-sun6i-a31.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "osc24M", 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUN6I_A31_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "osc24M", 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x284, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "osc24M", 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "osc24M", 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "osc24M", 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "osc24M", 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "osc24M", 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "osc24M", 0x038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * integer / fractional clock with switchable multipliers and dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * This is not supported here. We hardcode the PLL to MIPI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SUN6I_A31_PLL_MIPI_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pll_mipi_parents, 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 8, 4, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 21, 0, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) BIT(31) | BIT(23) | BIT(22), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "osc24M", 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "osc24M", 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const char * const cpux_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "pll-cpu", "pll-cpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_div_table axi_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .val = 4, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .val = 5, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .val = 6, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .val = 7, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x050, 0, 3, axi_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SUN6I_A31_AHB1_REG 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const ahb1_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "axi", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct clk_div_table apb1_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0x054, 8, 2, apb1_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const apb2_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "pll-periph", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x060, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0x060, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0x060, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0x060, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x060, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x060, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x060, BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x060, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x064, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x064, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x064, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x064, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x064, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x064, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x064, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x064, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x064, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x068, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x068, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x06c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x06c, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x088, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x088, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x08c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x08c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x090, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x090, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x094, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x094, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0x0cc, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x0cc, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0x0cc, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* TODO emac clk not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0x100, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x100, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0x100, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x100, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x100, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x100, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x100, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x100, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x100, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x100, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const char * const de_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "pll-periph-2x", "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "pll9", "pll10" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x104, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x108, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x10c, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x110, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const char * const mp_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "pll9", "pll10" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x114, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "pll-video1-2x", "pll-mipi" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "pll-video1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x12c, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x130, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "pll9", "pll10", "pll-mipi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "pll-ve" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x134, 16, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const u8 csi_mclk_table[] = { 0, 1, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct ccu_div csi0_mclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .enable = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .div = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .reg = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct ccu_div csi1_mclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .enable = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .div = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .reg = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x13c, 16, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0x148, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0x150, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const char * const mbus_parents[] = { "osc24M", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 0x168, 16, 3, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) lcd_ch1_parents, 0x168, 0, 3, 8, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) BIT(15), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x180, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0x184, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x188, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x18c, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "pll9", "pll10" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { .index = 1, .div = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static struct ccu_div gpu_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .div = _SUNXI_CCU_DIV(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .fixed_predivs = gpu_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .n_predivs = ARRAY_SIZE(gpu_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .reg = 0x1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) gpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct ccu_div gpu_memory_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .div = _SUNXI_CCU_DIV(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .fixed_predivs = gpu_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .n_predivs = ARRAY_SIZE(gpu_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .reg = 0x1a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) gpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct ccu_div gpu_hyd_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .div = _SUNXI_CCU_DIV(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .fixed_predivs = gpu_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .n_predivs = ARRAY_SIZE(gpu_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .reg = 0x1a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) gpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 0x1b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "axi", "ahb1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { .index = 0, .div = 750, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { .index = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { .index = 4, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct ccu_mp out_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .table = clk_out_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .fixed_predivs = clk_out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .n_predivs = ARRAY_SIZE(clk_out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .reg = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .hw.init = CLK_HW_INIT_PARENTS("out-a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) clk_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static struct ccu_mp out_b_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .table = clk_out_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .fixed_predivs = clk_out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .n_predivs = ARRAY_SIZE(clk_out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .reg = 0x304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .hw.init = CLK_HW_INIT_PARENTS("out-b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clk_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static struct ccu_mp out_c_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .table = clk_out_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .fixed_predivs = clk_out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .n_predivs = ARRAY_SIZE(clk_out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .reg = 0x308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .hw.init = CLK_HW_INIT_PARENTS("out-c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) clk_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static struct ccu_common *sun6i_a31_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) &pll_cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &pll_periph_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &pll_mipi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &pll9_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) &pll10_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) &ahb1_mipidsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) &ahb1_ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &ahb1_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) &ahb1_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &ahb1_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) &ahb1_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) &ahb1_mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &ahb1_nand1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &ahb1_nand0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &ahb1_sdram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &ahb1_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &ahb1_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) &ahb1_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) &ahb1_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) &ahb1_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &ahb1_spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) &ahb1_spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &ahb1_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) &ahb1_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) &ahb1_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &ahb1_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) &ahb1_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &ahb1_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) &ahb1_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) &ahb1_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &ahb1_lcd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &ahb1_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &ahb1_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) &ahb1_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) &ahb1_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &ahb1_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &ahb1_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &ahb1_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &ahb1_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &ahb1_deu0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &ahb1_deu1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &ahb1_drc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &ahb1_drc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) &apb1_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &apb1_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &apb1_digital_mic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &apb1_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &apb1_daudio0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &apb1_daudio1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &apb2_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) &apb2_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) &apb2_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &apb2_i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &apb2_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &apb2_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &apb2_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) &apb2_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &apb2_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &apb2_uart5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &nand0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &nand1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &mmc3_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &mmc3_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &daudio0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &daudio1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &usb_phy2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &usb_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &mdfs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) &sdram0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &sdram1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &dram_csi_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &dram_drc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &dram_drc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &dram_deu0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &dram_deu1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &dram_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) &dram_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) &dram_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &dram_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &dram_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &lcd0_ch0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &lcd1_ch0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) &lcd0_ch1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &lcd1_ch1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) &csi0_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) &csi0_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &csi1_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) &codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &digital_mic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) &hdmi_ddc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) &ps_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) &mbus0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) &mbus1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) &mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &mipi_dsi_dphy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) &mipi_csi_dphy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &iep_drc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &iep_drc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) &iep_deu0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) &iep_deu1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &gpu_core_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) &gpu_memory_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &gpu_hyd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &ats_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &trace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) &out_a_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &out_b_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &out_c_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* We hardcode the divider to 1 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [CLK_PLL9] = &pll9_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [CLK_PLL10] = &pll10_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [CLK_AHB1_SS] = &ahb1_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [CLK_AHB1_TS] = &ahb1_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [CLK_AHB1_VE] = &ahb1_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [CLK_AHB1_MP] = &ahb1_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [CLK_APB1_CODEC] = &apb1_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [CLK_APB1_PIO] = &apb1_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [CLK_APB2_UART0] = &apb2_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [CLK_APB2_UART1] = &apb2_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [CLK_APB2_UART2] = &apb2_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [CLK_APB2_UART3] = &apb2_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [CLK_APB2_UART4] = &apb2_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [CLK_APB2_UART5] = &apb2_uart5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [CLK_NAND0] = &nand0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [CLK_NAND1] = &nand1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [CLK_MMC3] = &mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [CLK_SPI3] = &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [CLK_DAUDIO0] = &daudio0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) [CLK_DAUDIO1] = &daudio1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [CLK_MDFS] = &mdfs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [CLK_SDRAM0] = &sdram0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [CLK_SDRAM1] = &sdram1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [CLK_BE0] = &be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [CLK_BE1] = &be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [CLK_FE0] = &fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [CLK_FE1] = &fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [CLK_MP] = &mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [CLK_PS] = &ps_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [CLK_MBUS0] = &mbus0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [CLK_MBUS1] = &mbus1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [CLK_ATS] = &ats_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [CLK_TRACE] = &trace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [CLK_OUT_A] = &out_a_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [CLK_OUT_B] = &out_b_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [CLK_OUT_C] = &out_c_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [RST_USB_PHY2] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [RST_AHB1_SS] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [RST_AHB1_TS] = { 0x2c0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [RST_AHB1_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) [RST_AHB1_MP] = { 0x2c4, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [RST_APB2_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [RST_APB2_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) [RST_APB2_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) [RST_APB2_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) [RST_APB2_UART4] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) [RST_APB2_UART5] = { 0x2d8, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .ccu_clks = sun6i_a31_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .hw_clks = &sun6i_a31_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .resets = sun6i_a31_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static struct ccu_mux_nb sun6i_a31_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .common = &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .cm = &cpu_clk.mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .delay_us = 1, /* > 8 clock cycles at 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .bypass_index = 1, /* index of 24 MHz oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static void __init sun6i_a31_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) val &= ~GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Force PLL-MIPI to MIPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) val &= BIT(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Force AHB1 to PLL6 / 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) val = readl(reg + SUN6I_A31_AHB1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* set PLL6 pre-div = 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) val &= ~GENMASK(7, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) val |= 0x2 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* select PLL6 / pre-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) val &= ~GENMASK(13, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) val |= 0x3 << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) writel(val, reg + SUN6I_A31_AHB1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) &sun6i_a31_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) sun6i_a31_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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