Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN5I_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN5I_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun5i-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/sun5i-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* The HOSC is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_CORE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO_BASE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_2X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_AUDIO_4X	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_AUDIO_8X	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PLL_VIDEO0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* The PLL_VIDEO0_2X is exported for HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_VE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_DDR_BASE	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_PLL_DDR		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_PLL_DDR_OTHER	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PLL_PERIPH		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_PLL_VIDEO1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The PLL_VIDEO1_2X is exported for HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* The CPU clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_AXI			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_AHB			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_APB0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_APB1		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_DRAM_AXI		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* AHB gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* APB0 gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* APB1 gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Modules clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* USB clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* GPS clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* DRAM gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* More display modules clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_TCON_CH1_SCLK	91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* The rest of the module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_NUMBER		(CLK_IEP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif /* _CCU_SUN5I_H_ */