^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_sdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu-sun5i.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct ccu_nkmp pll_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .hw.init = CLK_HW_INIT("pll-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN5I_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct ccu_nm pll_audio_base_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The datasheet is wrong here, this doesn't have any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x00c, BIT(31)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .reg = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .features = CCU_FEATURE_SIGMA_DELTA_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .hw.init = CLK_HW_INIT("pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct ccu_mult pll_video0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 270000000, 297000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .features = (CCU_FEATURE_FRACTIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CCU_FEATURE_ALL_PREDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .prediv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .hw.init = CLK_HW_INIT("pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct ccu_nkmp pll_ve_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .reg = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .hw.init = CLK_HW_INIT("pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct ccu_nk pll_ddr_base_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .hw.init = CLK_HW_INIT("pll-ddr-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct ccu_div pll_ddr_other_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct ccu_nk pll_periph_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .hw.init = CLK_HW_INIT("pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct ccu_mult pll_video1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 270000000, 297000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .reg = 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .features = (CCU_FEATURE_FRACTIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CCU_FEATURE_ALL_PREDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .prediv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .hw.init = CLK_HW_INIT("pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SUN5I_AHB_REG 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char * const cpu_parents[] = { "osc32k", "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "pll-core" , "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .index = 3, .div = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct ccu_mux cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .fixed_predivs = cpu_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .n_predivs = ARRAY_SIZE(cpu_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .hw.init = CLK_HW_INIT_PARENTS("cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct ccu_mux_fixed_prediv ahb_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .index = 2, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct ccu_div ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .fixed_predivs = ahb_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .n_predivs = ARRAY_SIZE(ahb_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .hw.init = CLK_HW_INIT_PARENTS("ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ahb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct clk_div_table apb0_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0x054, 8, 2, apb0_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x05c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x060, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x060, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x060, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0x060, BIT(14), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x060, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x060, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x060, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static SUNXI_CCU_GATE(ahb_tve_clk, "ahb-tve", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0x064, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static SUNXI_CCU_GATE(ahb_lcd_clk, "ahb-lcd", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static SUNXI_CCU_GATE(ahb_csi_clk, "ahb-csi", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static SUNXI_CCU_GATE(ahb_hdmi_clk, "ahb-hdmi", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static SUNXI_CCU_GATE(ahb_de_be_clk, "ahb-de-be", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static SUNXI_CCU_GATE(ahb_de_fe_clk, "ahb-de-fe", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x064, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static SUNXI_CCU_GATE(ahb_iep_clk, "ahb-iep", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x064, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x068, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x068, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x068, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const char * const mod0_default_parents[] = { "hosc", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const char * const spdif_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", spdif_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const char * const keypad_parents[] = { "hosc", "losc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const u8 keypad_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct ccu_mp keypad_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .reg = 0x0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .hw.init = CLK_HW_INIT_PARENTS("keypad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) keypad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x0cc, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const char * const gps_parents[] = { "hosc", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "pll-video1", "pll-ve" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0x0d0, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0x100, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static SUNXI_CCU_GATE(dram_tve_clk, "dram-tve", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x100, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x100, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x100, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x100, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static SUNXI_CCU_GATE(dram_iep_clk, "dram-iep", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x100, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const char * const de_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x104, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x10c, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "pll-video0-2x", "pll-video1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "pll-video0-2x", "pll-video1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) csi_parents, csi_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0x134, 0, 5, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0x13c, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static SUNXI_CCU_GATE(avs_clk, "avs", "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const u8 hdmi_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hdmi_parents, hdmi_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0x150, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const char * const gpu_parents[] = { "pll-video0", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "pll-ddr-other", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "pll-video1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 0x154, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const char * const mbus_parents[] = { "hosc", "pll-periph", "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static SUNXI_CCU_GATE(iep_clk, "iep", "de-be",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0x160, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct ccu_common *sun5i_a10s_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &hosc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) &pll_core_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &pll_ddr_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) &pll_ddr_other_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &pll_periph_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &ahb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &apb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &axi_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &ahb_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &ahb_ehci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &ahb_ohci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &ahb_ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &ahb_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &ahb_bist_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &ahb_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &ahb_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &ahb_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &ahb_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &ahb_sdram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &ahb_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) &ahb_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &ahb_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &ahb_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &ahb_spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &ahb_gps_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &ahb_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) &ahb_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) &ahb_tve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &ahb_lcd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &ahb_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &ahb_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &ahb_de_be_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &ahb_de_fe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &ahb_iep_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &ahb_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) &apb0_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) &apb0_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) &apb0_i2s_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &apb0_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &apb0_ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &apb0_keypad_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) &apb1_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &apb1_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) &apb1_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &apb1_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) &apb1_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) &apb1_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) &apb1_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) &ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) &ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) &i2s_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &keypad_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &usb_ohci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) &gps_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &dram_tve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) &dram_de_fe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &dram_de_be_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &dram_ace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) &dram_iep_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) &de_be_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) &de_fe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &tcon_ch0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) &tcon_ch1_sclk2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) &tcon_ch1_sclk1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) &csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &iep_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* We hardcode the divider to 1 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) [CLK_HOSC] = &hosc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [CLK_PLL_CORE] = &pll_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [CLK_AHB] = &ahb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [CLK_APB0] = &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) [CLK_AHB_HDMI] = &ahb_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) [CLK_APB0_I2S] = &apb0_i2s_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [CLK_IR] = &ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [CLK_I2S] = &i2s_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [CLK_KEYPAD] = &keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [CLK_GPS] = &gps_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [CLK_DE_BE] = &de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [CLK_DE_FE] = &de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [CLK_CSI] = &csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [CLK_IEP] = &iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [RST_GPS] = { 0x0d0, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [RST_DE_BE] = { 0x104, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [RST_DE_FE] = { 0x10c, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [RST_TVE] = { 0x118, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [RST_LCD] = { 0x118, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [RST_CSI] = { 0x134, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [RST_VE] = { 0x13c, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [RST_GPU] = { 0x154, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [RST_IEP] = { 0x160, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .ccu_clks = sun5i_a10s_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .hw_clks = &sun5i_a10s_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .resets = sun5i_a10s_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * The A13 is the A10s minus the TS, GPS, HDMI, I2S and the keypad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct clk_hw_onecell_data sun5i_a13_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [CLK_HOSC] = &hosc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [CLK_PLL_CORE] = &pll_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [CLK_AHB] = &ahb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [CLK_APB0] = &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [CLK_IR] = &ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [CLK_DE_BE] = &de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [CLK_DE_FE] = &de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [CLK_CSI] = &csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [CLK_IEP] = &iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct sunxi_ccu_desc sun5i_a13_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ccu_clks = sun5i_a10s_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .hw_clks = &sun5i_a13_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .resets = sun5i_a10s_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * The GR8 is the A10s CCU minus the HDMI and keypad, plus SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static struct clk_hw_onecell_data sun5i_gr8_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) [CLK_HOSC] = &hosc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [CLK_PLL_CORE] = &pll_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) [CLK_AHB] = &ahb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) [CLK_APB0] = &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) [CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) [CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) [CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) [CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) [CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) [CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [CLK_APB0_I2S] = &apb0_i2s_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) [CLK_IR] = &ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [CLK_I2S] = &i2s_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [CLK_GPS] = &gps_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [CLK_DE_BE] = &de_be_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [CLK_DE_FE] = &de_fe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [CLK_CSI] = &csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [CLK_IEP] = &iep_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const struct sunxi_ccu_desc sun5i_gr8_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .ccu_clks = sun5i_a10s_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .hw_clks = &sun5i_gr8_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .resets = sun5i_a10s_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static void __init sun5i_ccu_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) const struct sunxi_ccu_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val = readl(reg + SUN5I_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) val &= ~GENMASK(29, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * Use the peripheral PLL as the AHB parent, instead of CPU /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * AXI which have rate changes due to cpufreq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * This is especially a big deal for the HS timer whose parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * clock is AHB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) val = readl(reg + SUN5I_AHB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) val &= ~GENMASK(7, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) writel(val | (2 << 6), reg + SUN5I_AHB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) sunxi_ccu_probe(node, reg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static void __init sun5i_a10s_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sun5i_ccu_init(node, &sun5i_a10s_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) sun5i_a10s_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static void __init sun5i_a13_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sun5i_ccu_init(node, &sun5i_a13_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) CLK_OF_DECLARE(sun5i_a13_ccu, "allwinner,sun5i-a13-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) sun5i_a13_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void __init sun5i_gr8_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) sun5i_ccu_init(node, &sun5i_gr8_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) CLK_OF_DECLARE(sun5i_gr8_ccu, "nextthing,gr8-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) sun5i_gr8_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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