^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ccu-sun50i-h6.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * P should only be used for output frequencies lower than 288 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * For now we can just model it as a multiplier clock, and force P to /1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * The M factor is present in the register's description, but not in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * frequency formula, and it's documented as "M is only used for backdoor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * testing", so it's not modelled and then force to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN50I_H6_PLL_CPUX_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct ccu_mult pll_cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUN50I_H6_PLL_DDR0_REG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct ccu_nkmp pll_ddr0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUN50I_H6_PLL_PERIPH0_REG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct ccu_nkmp pll_periph0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUN50I_H6_PLL_PERIPH1_REG 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct ccu_nkmp pll_periph1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SUN50I_H6_PLL_GPU_REG 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct ccu_nkmp pll_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .reg = 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * For Video PLLs, the output divider is described as "used for testing"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * in the user manual. So it's not modelled and forced to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SUN50I_H6_PLL_VIDEO0_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct ccu_nm pll_video0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .min_rate = 288000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .max_rate = 2400000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .reg = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SUN50I_H6_PLL_VIDEO1_REG 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct ccu_nm pll_video1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .min_rate = 288000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .max_rate = 2400000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .reg = 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SUN50I_H6_PLL_VE_REG 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct ccu_nkmp pll_ve_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .reg = 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SUN50I_H6_PLL_DE_REG 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct ccu_nkmp pll_de_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .reg = 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .hw.init = CLK_HW_INIT("pll-de", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SUN50I_H6_PLL_HSIC_REG 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct ccu_nkmp pll_hsic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .reg = 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * The Audio PLL is supposed to have 3 outputs: 2 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * the base (2x and 4x), and one variable divider (the one true pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * We don't have any need for the variable divider for now, so we just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * hardcode it to match with the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SUN50I_H6_PLL_AUDIO_REG 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct ccu_nm pll_audio_base_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) BIT(24), 0x178, BIT(31)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .features = CCU_FEATURE_SIGMA_DELTA_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .reg = 0x078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const cpux_parents[] = { "osc24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "iosc", "pll-cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "iosc", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) psi_ahb1_ahb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "pll-ddr0", "pll-periph0-4x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x60c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char * const deinterlace_parents[] = { "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) deinterlace_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x62c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char * const gpu_parents[] = { "pll-gpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x67c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Also applies to EMCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x68c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char * const ve_parents[] = { "pll-ve" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x69c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x6bc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x6cc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x70c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x71c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x72c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x73c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x78c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x79c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const char * const dram_parents[] = { "pll-ddr0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct ccu_div dram_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .div = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .reg = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .hw.init = CLK_HW_INIT_PARENTS("dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x804, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x804, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x804, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x804, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x804, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x804, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x804, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x80c, BIT(0), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "pll-periph1", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "pll-periph1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "pll-periph1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const char * const ir_tx_parents[] = { "osc32k", "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 8, 2, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) BIT(31),/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct ccu_div i2s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .reg = 0xa0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .hw.init = CLK_HW_INIT_PARENTS("i2s3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct ccu_div i2s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .reg = 0xa10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .hw.init = CLK_HW_INIT_PARENTS("i2s0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct ccu_div i2s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .reg = 0xa14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .hw.init = CLK_HW_INIT_PARENTS("i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct ccu_div i2s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .reg = 0xa18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .hw.init = CLK_HW_INIT_PARENTS("i2s2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct ccu_div spdif_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .reg = 0xa20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .hw.init = CLK_HW_INIT_PARENTS("spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct ccu_div dmic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .reg = 0xa40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .hw.init = CLK_HW_INIT_PARENTS("dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct ccu_div audio_hub_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .reg = 0xa60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * We will force them to 0 (12M divided from 48M).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SUN50I_H6_USB0_CLK_REG 0xa70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SUN50I_H6_USB3_CLK_REG 0xa7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct clk_fixed_factor pll_periph0_4x_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) &pll_periph0_4x_clk.hw, 24, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 0xab0, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0xab0, BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "pll-periph0", 0xab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0xabc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const char * const hdmi_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "pll-video1-4x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { .index = 1, .div = 36621 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct ccu_mux hdmi_cec_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .fixed_predivs = hdmi_cec_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .n_predivs = ARRAY_SIZE(hdmi_cec_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .reg = 0xb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) hdmi_cec_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0xb5c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const char * const tcon_lcd0_parents[] = { "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "pll-video0-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tcon_lcd0_parents, 0xb60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0xb7c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const char * const tcon_tv0_parents[] = { "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "pll-video0-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "pll-video1-4x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) tcon_tv0_parents, 0xb80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 0xb9c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const u8 csi_top_table[] = { 0, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) csi_top_parents, csi_top_table, 0xc04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) csi_mclk_parents, 0xc08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Fixed factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * rates can be set exactly in conjunction with sigma-delta modulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 24, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 4, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const struct clk_hw *pll_periph0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) &pll_periph0_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pll_periph0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 1, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pll_periph0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct clk_hw *pll_periph1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) &pll_periph1_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pll_periph1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 1, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pll_periph1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 1, 4, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 1, 4, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static struct ccu_common *sun50i_h6_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &pll_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &cpux_apb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) &psi_ahb1_ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) &ahb3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) &deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) &bus_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) &emce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) &bus_emce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &vp9_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) &bus_vp9_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) &bus_psi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) &bus_pwm_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &bus_iommu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &mbus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) &mbus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) &mbus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &mbus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &mbus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &mbus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &mbus_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &nand0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &nand1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) &bus_i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &bus_scr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &bus_scr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &bus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &ir_tx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &bus_ir_tx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &bus_ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &i2s3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &bus_i2s3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &dmic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &bus_dmic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &audio_hub_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) &bus_audio_hub_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &usb_ohci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &usb_phy3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &usb_hsic_12m_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) &usb_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &bus_ohci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &bus_xhci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &bus_ehci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &pcie_ref_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &pcie_ref_out_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &pcie_maxi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) &pcie_aux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) &bus_pcie_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &hdmi_slow_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &hdmi_cec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &bus_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &bus_tcon_top_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &tcon_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &bus_tcon_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &tcon_tv0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &bus_tcon_tv0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) &csi_cci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &csi_top_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) &csi_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &hdcp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) &bus_hdcp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [CLK_OSC12M] = &osc12M_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [CLK_CPUX] = &cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [CLK_AHB3] = &ahb3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [CLK_EMCE] = &emce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [CLK_BUS_EMCE] = &bus_emce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [CLK_VP9] = &vp9_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [CLK_BUS_VP9] = &bus_vp9_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [CLK_BUS_PSI] = &bus_psi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [CLK_MBUS_TS] = &mbus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [CLK_MBUS_DEINTERLACE] = &mbus_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [CLK_NAND0] = &nand0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [CLK_NAND1] = &nand1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [CLK_BUS_TS] = &bus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [CLK_IR_TX] = &ir_tx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [CLK_BUS_THS] = &bus_ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [CLK_I2S3] = &i2s3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [CLK_DMIC] = &dmic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [CLK_BUS_XHCI] = &bus_xhci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [CLK_PCIE_REF_100M] = &pcie_ref_100m_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [CLK_PCIE_REF] = &pcie_ref_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [CLK_PCIE_REF_OUT] = &pcie_ref_out_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [CLK_PCIE_MAXI] = &pcie_maxi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [CLK_BUS_PCIE] = &bus_pcie_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [CLK_CSI_CCI] = &csi_cci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [CLK_CSI_TOP] = &csi_top_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [CLK_HDCP] = &hdcp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [RST_MBUS] = { 0x540, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [RST_BUS_DE] = { 0x60c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [RST_BUS_GPU] = { 0x67c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) [RST_BUS_CE] = { 0x68c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [RST_BUS_VE] = { 0x69c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [RST_BUS_EMCE] = { 0x6bc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [RST_BUS_VP9] = { 0x6cc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [RST_BUS_DMA] = { 0x70c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [RST_BUS_DBG] = { 0x78c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [RST_BUS_PSI] = { 0x79c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [RST_BUS_PWM] = { 0x7ac, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [RST_BUS_DRAM] = { 0x80c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [RST_BUS_NAND] = { 0x82c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [RST_BUS_MMC0] = { 0x84c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [RST_BUS_MMC1] = { 0x84c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [RST_BUS_MMC2] = { 0x84c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [RST_BUS_UART0] = { 0x90c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [RST_BUS_UART1] = { 0x90c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [RST_BUS_UART2] = { 0x90c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [RST_BUS_UART3] = { 0x90c, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [RST_BUS_I2C0] = { 0x91c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [RST_BUS_I2C1] = { 0x91c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [RST_BUS_I2C2] = { 0x91c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [RST_BUS_I2C3] = { 0x91c, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [RST_BUS_SCR0] = { 0x93c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [RST_BUS_SCR1] = { 0x93c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [RST_BUS_SPI0] = { 0x96c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [RST_BUS_SPI1] = { 0x96c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [RST_BUS_EMAC] = { 0x97c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [RST_BUS_TS] = { 0x9bc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [RST_BUS_THS] = { 0x9fc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [RST_BUS_I2S0] = { 0xa1c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [RST_BUS_I2S1] = { 0xa1c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [RST_BUS_I2S2] = { 0xa1c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [RST_BUS_I2S3] = { 0xa1c, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [RST_USB_PHY0] = { 0xa70, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [RST_USB_PHY1] = { 0xa74, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [RST_USB_PHY3] = { 0xa7c, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [RST_USB_HSIC] = { 0xa7c, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [RST_BUS_XHCI] = { 0xa8c, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [RST_BUS_OTG] = { 0xa8c, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [RST_BUS_PCIE] = { 0xabc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [RST_PCIE_POWERUP] = { 0xabc, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [RST_BUS_HDMI] = { 0xb1c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [RST_BUS_CSI] = { 0xc2c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [RST_BUS_HDCP] = { 0xc4c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const struct sunxi_ccu_desc sun50i_h6_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .ccu_clks = sun50i_h6_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .num_ccu_clks = ARRAY_SIZE(sun50i_h6_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .hw_clks = &sun50i_h6_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .resets = sun50i_h6_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .num_resets = ARRAY_SIZE(sun50i_h6_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static const u32 pll_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) SUN50I_H6_PLL_CPUX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) SUN50I_H6_PLL_DDR0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SUN50I_H6_PLL_PERIPH0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SUN50I_H6_PLL_PERIPH1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SUN50I_H6_PLL_GPU_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SUN50I_H6_PLL_VIDEO0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) SUN50I_H6_PLL_VIDEO1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SUN50I_H6_PLL_VE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SUN50I_H6_PLL_DE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SUN50I_H6_PLL_HSIC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) SUN50I_H6_PLL_AUDIO_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const u32 pll_video_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SUN50I_H6_PLL_VIDEO0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SUN50I_H6_PLL_VIDEO1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static const u32 usb2_clk_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SUN50I_H6_USB0_CLK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SUN50I_H6_USB3_CLK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int sun50i_h6_ccu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Enable the lock bits on all PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) val = readl(reg + pll_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) val |= BIT(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) writel(val, reg + pll_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Force the output divider of video PLLs to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * See the comment before pll-video0 definition for the reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) val = readl(reg + pll_video_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) val &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) writel(val, reg + pll_video_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * This clock mux is still mysterious, and the code just enforces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * it to have a valid clock parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) val = readl(reg + usb2_clk_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) val &= ~GENMASK(25, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) writel (val, reg + usb2_clk_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * Force the post-divider of pll-audio to 12 and the output divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * of it to 2, so 24576000 and 22579200 rates can be set exactly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) val &= ~(GENMASK(21, 16) | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * First clock parent (osc32K) is unusable for CEC. But since there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * is no good way to force parent switch (both run with same frequency),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * just set second clock parent here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) val |= BIT(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const struct of_device_id sun50i_h6_ccu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) { .compatible = "allwinner,sun50i-h6-ccu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct platform_driver sun50i_h6_ccu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .probe = sun50i_h6_ccu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .name = "sun50i-h6-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .of_match_table = sun50i_h6_ccu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) builtin_platform_driver(sun50i_h6_ccu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags