^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu-sun50i-h6-r.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * clock definitions in the BSP source code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "iosc", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { .index = 3, .shift = 0, .width = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct ccu_div ar100_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .var_predivs = ar100_r_apb2_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .hw.init = CLK_HW_INIT_PARENTS("ar100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ar100_r_apb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct ccu_div r_apb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .var_predivs = ar100_r_apb2_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ar100_r_apb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Information about the gate/resets are gathered from the clock header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * in the BSP source code, although most of them are unused. The existence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * of the hardware block is verified with "3.1 Memory Mapping" chapter in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * with "3.3.2.1 System Bus Tree" chapter inthe same document.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x11c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x12c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x13c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x18c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x19c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x1cc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x1ec, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Information of IR(RX) mod clock is gathered from BSP source code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) r_mod0_default_parents, 0x1c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * BSP didn't use the 1-wire function at all now, and the information about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * this mod clock is guessed from the IR mod clock above. The existence of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * this mod clock is proven by BSP clock header, and the dividers are verified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * by contents in the 1-wire related chapter of the User Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) r_mod0_default_parents, 0x1e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &ar100_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &r_apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) &r_apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &r_apb1_timer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &r_apb1_twd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &r_apb1_pwm_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &r_apb2_uart_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &r_apb2_i2c_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &r_apb1_ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) &r_apb1_w1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &w1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [CLK_AR100] = &ar100_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [CLK_R_AHB] = &r_ahb_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [CLK_R_APB1] = &r_apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [CLK_R_APB2] = &r_apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [CLK_IR] = &ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [CLK_W1] = &w1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [RST_R_APB1_PWM] = { 0x13c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [RST_R_APB2_UART] = { 0x18c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .ccu_clks = sun50i_h6_r_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .hw_clks = &sun50i_h6_r_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .resets = sun50i_h6_r_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void __init sunxi_r_ccu_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const struct sunxi_ccu_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sunxi_ccu_probe(node, reg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sun50i_h6_r_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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