Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN50I_A64_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN50I_A64_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun50i-a64-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/sun50i-a64-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_OSC_12M			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_CPUX			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO_BASE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_2X		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_AUDIO_4X		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_AUDIO_8X		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* PLL_VIDEO0 exported for HDMI PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_VIDEO0_2X		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_VE			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_DDR0			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* PLL_PERIPH0 exported for PRCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_PLL_PERIPH0_2X		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_PLL_PERIPH1			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_PLL_PERIPH1_2X		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_PLL_VIDEO1			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_PLL_GPU			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_PLL_MIPI			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_PLL_HSIC			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_PLL_DE			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_PLL_DDR1			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_AXI				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_APB				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_AHB1			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_APB1			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_APB2			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_AHB2			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* All the bus gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* The first bunch of module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_USB_OHCI0_12M		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_USB_OHCI1_12M		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_DRAM			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* All the DRAM gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* And the DSI and GPU module clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_NUMBER			(CLK_GPU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif /* _CCU_SUN50I_A64_H_ */