^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu-sun50i-a64.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct ccu_nkmp pll_cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .hw.init = CLK_HW_INIT("pll-cpux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN50I_A64_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "osc24M", 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x284, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "osc24M", 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 192000000, /* Minimum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1008000000, /* Maximum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "osc24M", 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "osc24M", 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct ccu_nk pll_periph0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &ccu_nk_ops, CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct ccu_nk pll_periph1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .reg = 0x02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &ccu_nk_ops, CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "osc24M", 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 192000000, /* Minimum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 1008000000, /* Maximum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "osc24M", 0x038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * The output function can be changed to something more complex that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * we do not handle yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Hardcode the mode so that we don't fall in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SUN50I_A64_PLL_MIPI_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct ccu_nkm pll_mipi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * user manual, and by experiments the PLL doesn't work without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * these bits toggled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .enable = BIT(31) | BIT(23) | BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .n = _SUNXI_CCU_MULT(8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .m = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .reg = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "osc24M", 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "osc24M", 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "osc24M", 0x04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const char * const cpux_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "pll-cpux", "pll-cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const ahb1_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "axi", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct clk_div_table apb1_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x054, 8, 2, apb1_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char * const apb2_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .index = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct ccu_mux ahb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .fixed_predivs = ahb2_fixed_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .reg = 0x05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .hw.init = CLK_HW_INIT_PARENTS("ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ahb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x060, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x060, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x060, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 0x060, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x064, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x064, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x064, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x064, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x068, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x068, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x068, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x06c, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x070, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct clk_div_table ths_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .val = 3, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const char * const ths_parents[] = { "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct ccu_div ths_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .reg = 0x074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .hw.init = CLK_HW_INIT_PARENTS("ths",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ths_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * MMC clocks are the new timing mode (see A83T & H3) variety, but without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * the mode switch. This means they have a 2x post divider between the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * and the MMC module. This is not documented in the manual, but is taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * into consideration when setting the mmc module clocks in the BSP kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Without it, MMC performance is degraded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * We model it here to be consistent with other SoCs supporting this mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * The alternative would be to add the 2x multiplier when setting the MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * module clock in the MMC driver, just for the A64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "pll-periph1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mmc_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mmc_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mmc_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 0x0cc, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0x0cc, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0x0cc, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x100, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x100, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x104, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const u8 tcon0_table[] = { 0, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) tcon0_table, 0x118, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const u8 tcon1_table[] = { 0, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct ccu_div tcon1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .div = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .reg = 0x11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hw.init = CLK_HW_INIT_PARENTS("tcon1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tcon1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x124, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x130, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x134, 16, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x134, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x140, BIT(30), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0x154, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "pll-ddr0", "pll-ddr1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const u8 dsi_dphy_table[] = { 0, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dsi_dphy_parents, dsi_dphy_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Fixed Factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* We hardcode the divider to 1 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct ccu_common *sun50i_a64_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) &pll_mipi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) &pll_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &pll_ddr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &bus_mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) &bus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &bus_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &bus_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &bus_tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &bus_tcon1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) &bus_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &bus_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) &bus_ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &bus_scr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &bus_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) &usb_hsic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) &usb_hsic_12m_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &dram_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &tcon1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) &csi_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &ac_dig_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) &ac_dig_4x_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) &hdmi_ddc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) &dsi_dphy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [CLK_OSC_12M] = &osc12M_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [CLK_CPUX] = &cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [CLK_BUS_TS] = &bus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [CLK_BUS_THS] = &bus_ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [CLK_THS] = &ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [CLK_TCON0] = &tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [CLK_TCON1] = &tcon1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [CLK_AC_DIG] = &ac_dig_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) [RST_USB_HSIC] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) [RST_DRAM] = { 0x0f4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) [RST_BUS_CE] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) [RST_BUS_NAND] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) [RST_BUS_TS] = { 0x2c0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) [RST_BUS_OTG] = { 0x2c0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) [RST_BUS_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [RST_BUS_DBG] = { 0x2c4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [RST_BUS_THS] = { 0x2d0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [RST_BUS_SCR] = { 0x2d8, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [RST_BUS_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [RST_BUS_UART4] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .ccu_clks = sun50i_a64_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .hw_clks = &sun50i_a64_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .resets = sun50i_a64_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .common = &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* copy from pll_cpux_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct ccu_mux_nb sun50i_a64_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .common = &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .cm = &cpux_clk.mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .delay_us = 1, /* > 8 clock cycles at 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .bypass_index = 1, /* index of 24 MHz oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int sun50i_a64_ccu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) val &= ~GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Gate then ungate PLL CPU after any rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Reparent CPU during PLL CPU rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) &sun50i_a64_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const struct of_device_id sun50i_a64_ccu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { .compatible = "allwinner,sun50i-a64-ccu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct platform_driver sun50i_a64_ccu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .probe = sun50i_a64_ccu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .name = "sun50i-a64-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .of_match_table = sun50i_a64_ccu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) builtin_platform_driver(sun50i_a64_ccu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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