Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _CCU_SUN50I_A100_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _CCU_SUN50I_A100_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <dt-bindings/clock/sun50i-a100-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/reset/sun50i-a100-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_OSC12M		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_PLL_CPUX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PLL_DDR0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PLL_PERIPH0 exported for PRCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_PERIPH0_2X	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_PERIPH1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_PERIPH1_2X	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PLL_GPU		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PLL_VIDEO0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PLL_VIDEO0_2X	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_VIDEO0_4X	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_VIDEO1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_VIDEO1_2X	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_PLL_VIDEO1_4X	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_PLL_VIDEO2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PLL_VIDEO2_2X	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_PLL_VIDEO2_4X	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_PLL_VIDEO3		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_PLL_VIDEO3_2X	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_PLL_VIDEO3_4X	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_PLL_VE		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_PLL_COM		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_PLL_COM_AUDIO	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_PLL_AUDIO		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* CPUX clock exported for DVFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_AXI			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_CPUX_APB		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_PSI_AHB1_AHB2	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_AHB3		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* APB1 clock exported for PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_APB2		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* All module clocks and bus gates are exported except DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_BUS_DRAM		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_NUMBER		(CLK_CSI_ISP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif /* _CCU_SUN50I_A100_H_ */