^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu-sun50i-a100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUN50I_A100_PLL_OUTPUT_ENABLE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN50I_A100_PLL_LOCK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN50I_A100_PLL_LOCK_ENABLE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN50I_A100_PLL_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN50I_A100_PLL_PERIPH1_PATTERN0 0xd1303333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * P should only be used for output frequencies lower than 288 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * For now we can just model it as a multiplier clock, and force P to /1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The M factor is present in the register's description, but not in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * frequency formula, and it's documented as "M is only used for backdoor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * testing", so it's not modelled and then force to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUN50I_A100_PLL_CPUX_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct ccu_mult pll_cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUN50I_A100_PLL_DDR0_REG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct ccu_nkmp pll_ddr0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_SET_RATE_UNGATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUN50I_A100_PLL_PERIPH0_REG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct ccu_nkmp pll_periph0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .hw.init = CLK_HW_INIT("pll-periph0", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SUN50I_A100_PLL_PERIPH1_REG 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct ccu_nkmp pll_periph1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .hw.init = CLK_HW_INIT("pll-periph1", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SUN50I_A100_PLL_PERIPH1_PATTERN0_REG 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SUN50I_A100_PLL_GPU_REG 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct ccu_nkmp pll_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .reg = 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .hw.init = CLK_HW_INIT("pll-gpu", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * For Video PLLs, the output divider is described as "used for testing"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * in the user manual. So it's not modelled and forced to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SUN50I_A100_PLL_VIDEO0_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct ccu_nm pll_video0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .reg = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .hw.init = CLK_HW_INIT("pll-video0", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SUN50I_A100_PLL_VIDEO1_REG 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct ccu_nm pll_video1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .reg = 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .hw.init = CLK_HW_INIT("pll-video1", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SUN50I_A100_PLL_VIDEO2_REG 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct ccu_nm pll_video2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .reg = 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .hw.init = CLK_HW_INIT("pll-video2", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SUN50I_A100_PLL_VE_REG 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct ccu_nkmp pll_ve_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .reg = 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .hw.init = CLK_HW_INIT("pll-ve", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * The COM PLL has m0 dividers in addition to the usual N, M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * factors. Since we only need 1 frequencies from this PLL: 45.1584 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * ignore it for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SUN50I_A100_PLL_COM_REG 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct ccu_sdm_setting pll_com_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct ccu_nm pll_com_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .m = _SUNXI_CCU_DIV(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .sdm = _SUNXI_CCU_SDM(pll_com_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x160, BIT(31)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .reg = 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .features = CCU_FEATURE_SIGMA_DELTA_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .hw.init = CLK_HW_INIT("pll-com", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SUN50I_A100_PLL_VIDEO3_REG 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct ccu_nm pll_video3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .fixed_post_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .reg = 0x068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .hw.init = CLK_HW_INIT("pll-video3", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * The Audio PLL has m0, m1 dividers in addition to the usual N, M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * factors. Since we only need 4 frequencies from this PLL: 22.5792 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * 24.576 MHz, 90.3168MHz and 98.304MHz ignore them for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Enforce the default for them, which is m0 = 1, m1 = 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SUN50I_A100_PLL_AUDIO_REG 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct ccu_nm pll_audio_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .lock = SUN50I_A100_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .m = _SUNXI_CCU_DIV(16, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x178, BIT(31)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .reg = 0x078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .features = CCU_FEATURE_FIXED_POSTDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CCU_FEATURE_SIGMA_DELTA_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .hw.init = CLK_HW_INIT("pll-audio", "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char * const cpux_parents[] = { "dcxo24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "iosc", "pll-cpux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const char * const psi_ahb1_ahb2_parents[] = { "dcxo24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "iosc", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) psi_ahb1_ahb2_parents, 0x510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const char * const ahb3_apb1_apb2_parents[] = { "dcxo24M", "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const char * const mbus_parents[] = { "dcxo24M", "pll-ddr0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const char * const de_parents[] = { "pll-com", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de0", de_parents, 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x60c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const char * const g2d_parents[] = { "pll-com", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "pll-video0-2x", "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "pll-video2-2x"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) g2d_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x63c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const char * const gpu_parents[] = { "pll-gpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x67c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const char * const ce_parents[] = { "dcxo24M", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x68c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char * const ve_parents[] = { "pll-ve" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0, 3, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 24, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x69c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x70c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x71c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x72c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x73c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x78c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x79c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x804, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x804, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x804, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x804, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x804, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static SUNXI_CCU_GATE(mbus_isp_clk, "mbus-isp", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0x804, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x804, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x80c, BIT(0), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const char * const nand_spi_parents[] = { "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "pll-periph1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "pll-periph1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const mmc_parents[] = { "dcxo24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "pll-periph1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CLK_SET_RATE_NO_REPARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CLK_SET_RATE_NO_REPARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK_SET_RATE_NO_REPARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", nand_spi_parents, 0x948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BIT(31) | BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const char * const ir_parents[] = { "osc32k", "iosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static SUNXI_CCU_MP_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_parents, 0x990,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static SUNXI_CCU_GATE(bus_ir_rx_clk, "bus-ir-rx", "ahb3", 0x99c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const char * const audio_parents[] = { "pll-audio", "pll-com-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct ccu_div i2s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .reg = 0xa10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .hw.init = CLK_HW_INIT_PARENTS("i2s0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct ccu_div i2s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .reg = 0xa14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .hw.init = CLK_HW_INIT_PARENTS("i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static struct ccu_div i2s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .reg = 0xa18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .hw.init = CLK_HW_INIT_PARENTS("i2s2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct ccu_div i2s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .reg = 0xa1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .hw.init = CLK_HW_INIT_PARENTS("i2s3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa20, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct ccu_div spdif_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .reg = 0xa24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .hw.init = CLK_HW_INIT_PARENTS("spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct ccu_div dmic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .reg = 0xa40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .hw.init = CLK_HW_INIT_PARENTS("dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) audio_parents, 0xa50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) audio_parents, 0xa54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) audio_parents, 0xa58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * We will force them to 0 (12M divided from 48M).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define SUN50I_A100_USB0_CLK_REG 0xa70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SUN50I_A100_USB1_CLK_REG 0xa74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static SUNXI_CCU_GATE(bus_dpss_top0_clk, "bus-dpss-top0", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0xabc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static SUNXI_CCU_GATE(bus_dpss_top1_clk, "bus-dpss-top1", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 0xacc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const char * const mipi_dsi_parents[] = { "dcxo24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mipi_dsi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0xb24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0xb4c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const char * const tcon_lcd_parents[] = { "pll-video0-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "pll-video1-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "pll-video2-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "pll-video3-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) tcon_lcd_parents, 0xb60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static SUNXI_CCU_GATE(bus_tcon_lcd_clk, "bus-tcon-lcd0", "ahb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 0xb7c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const char * const ledc_parents[] = { "dcxo24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static SUNXI_CCU_MP_WITH_MUX_GATE(ledc_clk, "ledc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ledc_parents, 0xbf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 8, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "ahb3", 0xbfc, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const char * const csi_top_parents[] = { "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "pll-video2-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "pll-video3-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) csi_top_parents, 0xc04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const char * const csi0_mclk_parents[] = { "dcxo24M", "pll-video2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "pll-video3", "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) csi0_mclk_parents, 0xc08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const char * const csi1_mclk_parents[] = { "dcxo24M", "pll-video3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "pll-video2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) csi1_mclk_parents, 0xc0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc1c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const char * const csi_isp_parents[] = { "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "pll-video2-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "pll-video3-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static SUNXI_CCU_M_WITH_MUX_GATE(csi_isp_clk, "csi-isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) csi_isp_parents, 0xc20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 24, 3, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Fixed factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static CLK_FIXED_FACTOR_HW(pll_com_audio_clk, "pll-com-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) &pll_com_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 5, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct clk_hw *pll_video0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) &pll_video0_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static CLK_FIXED_FACTOR_HWS(pll_video0_4x_clk, "pll-video0-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pll_video0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 1, 4, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pll_video0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const struct clk_hw *pll_video1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) &pll_video1_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static CLK_FIXED_FACTOR_HWS(pll_video1_4x_clk, "pll-video1-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pll_video1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 1, 4, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pll_video1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct clk_hw *pll_video2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) &pll_video2_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static CLK_FIXED_FACTOR_HWS(pll_video2_4x_clk, "pll-video2-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pll_video2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 1, 4, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static CLK_FIXED_FACTOR_HWS(pll_video2_2x_clk, "pll-video2-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pll_video2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const struct clk_hw *pll_video3_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &pll_video3_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static CLK_FIXED_FACTOR_HWS(pll_video3_4x_clk, "pll-video3-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pll_video3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 1, 4, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static CLK_FIXED_FACTOR_HWS(pll_video3_2x_clk, "pll-video3-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pll_video3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct ccu_common *sun50i_a100_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) &pll_video2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) &pll_video3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &pll_com_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) &pll_audio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) &cpux_apb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &psi_ahb1_ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) &ahb3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &g2d_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &bus_g2d_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) &bus_psi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) &bus_pwm_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &bus_iommu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &mbus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &mbus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) &mbus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) &mbus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &mbus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &mbus_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &mbus_g2d_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &nand0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &nand1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &bus_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) &bus_i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &bus_spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &emac_25m_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &ir_rx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &bus_ir_rx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &ir_tx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &bus_ir_tx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &bus_gpadc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &bus_ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &i2s3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &bus_i2s3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &dmic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) &bus_dmic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &audio_codec_dac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &audio_codec_adc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) &audio_codec_4x_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &bus_audio_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &bus_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &bus_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &bus_lradc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &bus_dpss_top0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &bus_dpss_top1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) &mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) &bus_mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &tcon_lcd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &bus_tcon_lcd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &ledc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &bus_ledc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &csi_top_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &csi0_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &csi1_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &csi_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static struct clk_hw_onecell_data sun50i_a100_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [CLK_OSC12M] = &osc12M_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) [CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) [CLK_PLL_VIDEO2_2X] = &pll_video2_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) [CLK_PLL_VIDEO3] = &pll_video3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [CLK_PLL_VIDEO3_2X] = &pll_video3_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [CLK_PLL_VIDEO3_4X] = &pll_video3_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [CLK_PLL_COM] = &pll_com_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [CLK_PLL_COM_AUDIO] = &pll_com_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [CLK_CPUX] = &cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [CLK_AHB3] = &ahb3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [CLK_G2D] = &g2d_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [CLK_BUS_PSI] = &bus_psi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [CLK_NAND0] = &nand0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [CLK_NAND1] = &nand1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [CLK_EMAC_25M] = &emac_25m_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [CLK_IR_RX] = &ir_rx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [CLK_BUS_IR_RX] = &bus_ir_rx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [CLK_IR_TX] = &ir_tx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [CLK_BUS_THS] = &bus_ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [CLK_I2S3] = &i2s3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [CLK_DMIC] = &dmic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [CLK_AUDIO_DAC] = &audio_codec_dac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [CLK_AUDIO_ADC] = &audio_codec_adc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [CLK_AUDIO_4X] = &audio_codec_4x_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [CLK_BUS_DPSS_TOP1] = &bus_dpss_top1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [CLK_TCON_LCD] = &tcon_lcd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [CLK_BUS_TCON_LCD] = &bus_tcon_lcd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [CLK_LEDC] = &ledc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [CLK_CSI_TOP] = &csi_top_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [CLK_CSI_ISP] = &csi_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static struct ccu_reset_map sun50i_a100_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [RST_MBUS] = { 0x540, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [RST_BUS_DE] = { 0x60c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [RST_BUS_G2D] = { 0x63c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [RST_BUS_GPU] = { 0x67c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [RST_BUS_CE] = { 0x68c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [RST_BUS_VE] = { 0x69c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [RST_BUS_DMA] = { 0x70c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [RST_BUS_DBG] = { 0x78c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [RST_BUS_PSI] = { 0x79c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [RST_BUS_PWM] = { 0x7ac, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [RST_BUS_DRAM] = { 0x80c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [RST_BUS_NAND] = { 0x82c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [RST_BUS_MMC0] = { 0x84c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [RST_BUS_MMC1] = { 0x84c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [RST_BUS_MMC2] = { 0x84c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) [RST_BUS_UART0] = { 0x90c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [RST_BUS_UART1] = { 0x90c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [RST_BUS_UART2] = { 0x90c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [RST_BUS_UART3] = { 0x90c, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [RST_BUS_UART4] = { 0x90c, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [RST_BUS_I2C0] = { 0x91c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [RST_BUS_I2C1] = { 0x91c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [RST_BUS_I2C2] = { 0x91c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [RST_BUS_I2C3] = { 0x91c, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [RST_BUS_SPI0] = { 0x96c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [RST_BUS_SPI1] = { 0x96c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [RST_BUS_SPI2] = { 0x96c, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [RST_BUS_EMAC] = { 0x97c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [RST_BUS_IR_RX] = { 0x99c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [RST_BUS_THS] = { 0x9fc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [RST_BUS_I2S0] = { 0xa20, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [RST_BUS_I2S1] = { 0xa20, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [RST_BUS_I2S2] = { 0xa20, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [RST_BUS_I2S3] = { 0xa20, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [RST_USB_PHY0] = { 0xa70, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [RST_USB_PHY1] = { 0xa74, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [RST_BUS_OTG] = { 0xa8c, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [RST_BUS_DPSS_TOP0] = { 0xabc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [RST_BUS_DPSS_TOP1] = { 0xacc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [RST_BUS_TCON_LCD] = { 0xb7c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [RST_BUS_LVDS] = { 0xbac, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [RST_BUS_CSI] = { 0xc1c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [RST_BUS_CSI_ISP] = { 0xc2c, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const struct sunxi_ccu_desc sun50i_a100_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .ccu_clks = sun50i_a100_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .num_ccu_clks = ARRAY_SIZE(sun50i_a100_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .hw_clks = &sun50i_a100_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .resets = sun50i_a100_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .num_resets = ARRAY_SIZE(sun50i_a100_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const u32 sun50i_a100_pll_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) SUN50I_A100_PLL_CPUX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SUN50I_A100_PLL_DDR0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SUN50I_A100_PLL_PERIPH0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SUN50I_A100_PLL_PERIPH1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) SUN50I_A100_PLL_GPU_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SUN50I_A100_PLL_VIDEO0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SUN50I_A100_PLL_VIDEO1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SUN50I_A100_PLL_VIDEO2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SUN50I_A100_PLL_VIDEO3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SUN50I_A100_PLL_VE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SUN50I_A100_PLL_COM_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SUN50I_A100_PLL_AUDIO_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const u32 sun50i_a100_pll_video_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) SUN50I_A100_PLL_VIDEO0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) SUN50I_A100_PLL_VIDEO1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) SUN50I_A100_PLL_VIDEO2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) SUN50I_A100_PLL_VIDEO3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const u32 sun50i_a100_usb2_clk_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SUN50I_A100_USB0_CLK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SUN50I_A100_USB1_CLK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static struct ccu_pll_nb sun50i_a100_pll_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .common = &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* copy from pll_cpux_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .enable = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static struct ccu_mux_nb sun50i_a100_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .common = &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .cm = &cpux_clk.mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .delay_us = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .bypass_index = 4, /* index of pll periph0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static int sun50i_a100_ccu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * Enable lock and enable bits on all PLLs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * Due to the current design, multiple PLLs share one power switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * so switching PLL is easy to cause stability problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * When initializing, we enable them by default. When disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * we only turn off the output of PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) val = readl(reg + sun50i_a100_pll_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) val |= SUN50I_A100_PLL_LOCK_ENABLE | SUN50I_A100_PLL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) writel(val, reg + sun50i_a100_pll_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * In order to pass the EMI certification, the SDM function of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * the peripheral 1 bus is enabled, and the frequency is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * calculated using the previous division factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) writel(SUN50I_A100_PLL_PERIPH1_PATTERN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) val = readl(reg + SUN50I_A100_PLL_PERIPH1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) val |= SUN50I_A100_PLL_SDM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) writel(val, reg + SUN50I_A100_PLL_PERIPH1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * Force the output divider of video PLLs to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * See the comment before pll-video0 definition for the reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_video_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) val = readl(reg + sun50i_a100_pll_video_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) val &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) writel(val, reg + sun50i_a100_pll_video_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * Enforce m1 = 0, m0 = 1 for Audio PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * See the comment before pll-audio definition for the reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) val = readl(reg + SUN50I_A100_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) val &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) val |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) writel(val, reg + SUN50I_A100_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * This clock mux is still mysterious, and the code just enforces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * it to have a valid clock parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) for (i = 0; i < ARRAY_SIZE(sun50i_a100_usb2_clk_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) val = readl(reg + sun50i_a100_usb2_clk_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) val &= ~GENMASK(25, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) writel(val, reg + sun50i_a100_usb2_clk_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a100_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Gate then ungate PLL CPU after any rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ccu_pll_notifier_register(&sun50i_a100_pll_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Reparent CPU during PLL CPU rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) &sun50i_a100_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const struct of_device_id sun50i_a100_ccu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { .compatible = "allwinner,sun50i-a100-ccu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static struct platform_driver sun50i_a100_ccu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .probe = sun50i_a100_ccu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .name = "sun50i-a100-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .of_match_table = sun50i_a100_ccu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) module_platform_driver(sun50i_a100_ccu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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