Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2017 Priit Laes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Priit Laes <plaes@plaes.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN4I_A10_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN4I_A10_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun4i-a10-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/sun7i-a20-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/reset/sun4i-a10-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* The HOSC is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_CORE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO_BASE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_AUDIO_2X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_AUDIO_4X	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PLL_AUDIO_8X	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PLL_VIDEO0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* The PLL_VIDEO0_2X clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_VE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_DDR_BASE	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_DDR		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_PLL_DDR_OTHER	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_PLL_PERIPH_BASE	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PLL_PERIPH		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_PLL_PERIPH_SATA	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_PLL_VIDEO1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The PLL_VIDEO1_2X clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_PLL_GPU		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* The CPU clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_AXI			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_AXI_DRAM		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_AHB			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_APB0		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_APB1		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* AHB gates are exported (23..68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* APB0 gates are exported (69..78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* APB1 gates are exported (79..95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* IP module clocks are exported (96..128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* DRAM gates are exported (129..142)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Media (display engine clocks & etc) are exported (143..169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_NUMBER_SUN4I	(CLK_MBUS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_NUMBER_SUN7I	(CLK_OUT_B + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif /* _CCU_SUN4I_A10_H_ */