^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2017 Maxime Ripard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Jonathan Liu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu_sdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ccu-sun4i-a10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct ccu_nkmp pll_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .hw.init = CLK_HW_INIT("pll-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN4I_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct ccu_nm pll_audio_base_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x00c, BIT(31)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .reg = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .features = CCU_FEATURE_SIGMA_DELTA_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .hw.init = CLK_HW_INIT("pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct ccu_mult pll_video0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 270000000, 297000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .features = (CCU_FEATURE_FRACTIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CCU_FEATURE_ALL_PREDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .prediv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .hw.init = CLK_HW_INIT("pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct ccu_nkmp pll_ve_sun4i_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .reg = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .hw.init = CLK_HW_INIT("pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct ccu_nk pll_ve_sun7i_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .reg = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .hw.init = CLK_HW_INIT("pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct ccu_nk pll_ddr_base_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .hw.init = CLK_HW_INIT("pll-ddr-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct ccu_div pll_ddr_other_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct ccu_nk pll_periph_base_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .hw.init = CLK_HW_INIT("pll-periph-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &pll_periph_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Not documented on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct ccu_div pll_periph_sata_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .enable = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .div = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .fixed_post_div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .hw.init = CLK_HW_INIT("pll-periph-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "pll-periph-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) &ccu_div_ops, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct ccu_mult pll_video1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 270000000, 297000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .reg = 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .features = (CCU_FEATURE_FRACTIONAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CCU_FEATURE_ALL_PREDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .prediv = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .hw.init = CLK_HW_INIT("pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct ccu_nk pll_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .reg = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .hw.init = CLK_HW_INIT("pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const char *const cpu_parents[] = { "osc32k", "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "pll-core", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .index = 3, .div = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SUN4I_AHB_REG 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct ccu_mux cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .fixed_predivs = cpu_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .n_predivs = ARRAY_SIZE(cpu_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .hw.init = CLK_HW_INIT_PARENTS("cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) cpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct ccu_div ahb_sun4i_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .index = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct ccu_div ahb_sun7i_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .fixed_predivs = ahb_sun7i_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .n_predivs = ARRAY_SIZE(ahb_sun7i_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .hw.init = CLK_HW_INIT_PARENTS("ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ahb_sun7i_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct clk_div_table apb0_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x054, 8, 2, apb0_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Not present on A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x05c, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x060, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x060, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x060, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x060, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x060, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x060, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x060, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x060, BIT(14), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 0x060, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x060, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x060, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x060, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Not documented on A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x060, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Not present on A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x060, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x064, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x064, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x064, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x064, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x064, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x064, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x064, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x064, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x064, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x064, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x064, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0x068, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x068, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x068, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x068, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x068, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x068, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0x068, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x06c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x06c, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0x06c, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x06c, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x06c, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x06c, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0x06c, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x06c, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x06c, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Undocumented on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* MMC output and sample clocks are not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0x088, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0x088, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* MMC output and sample clocks are not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 0x08c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x08c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* MMC output and sample clocks are not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0x090, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0x090, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* MMC output and sample clocks are not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0x094, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x094, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Undocumented on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* TODO: Check whether A10 actually supports osc32k as 4th parent? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "pll-ddr-other", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Undocumented on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const char *const keypad_parents[] = { "hosc", "losc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const u8 keypad_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct ccu_mp keypad_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .m = _SUNXI_CCU_DIV(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .reg = 0x0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .hw.init = CLK_HW_INIT_PARENTS("keypad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) keypad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * SATA supports external clock as parent via BIT(24) and is probably an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * optional crystal or oscillator that can be connected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * SATA-CLKM / SATA-CLKP pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 0x0cc, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 0x0cc, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* TODO: GPS CLK 0x0d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Not present on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 0x100, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 0x100, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 0x100, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 0x100, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0x100, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Clock seems to be critical only on sun4i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0x100, BIT(15), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0x100, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0x100, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0x100, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0x100, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0x100, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 0x100, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const char *const de_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0x104, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 0x108, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 0x10c, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0x110, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Undocumented on A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 0x114, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const char *const disp_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "pll-video0-2x", "pll-video1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "pll-ddr-other", "pll-periph" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) csi_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0x120, 0, 4, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* TVD clock setup for A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 0x128, 24, 1, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* TVD clock setup for A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "tvd-sclk2", tvd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 16, 4, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 8, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) BIT(15), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 0x128, 0, 4, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) disp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 0x12c, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 0x12c, 11, 1, BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) disp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 0x130, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0x130, 11, 1, BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "pll-video0-2x", "pll-video1-2x"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const u8 csi_table[] = { 0, 1, 2, 5, 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) csi_parents, csi_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 0x134, 0, 5, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) csi_parents, csi_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 0x138, 0, 5, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 0x148, 0, 4, 24, 1, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 0x150, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "pll-ddr-other",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 0x154, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "pll-ddr-other", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "pll-gpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) gpu_parents_sun7i, gpu_table_sun7i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 0x154, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "pll-ddr-other" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const u8 hdmi1_table[] = { 0, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) hdmi1_parents, hdmi1_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 0x17c, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .index = 0, .div = 750, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static struct ccu_mp out_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .fixed_predivs = clk_out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .n_predivs = ARRAY_SIZE(clk_out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .reg = 0x1f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .hw.init = CLK_HW_INIT_PARENTS("out-a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static struct ccu_mp out_b_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .fixed_predivs = clk_out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .n_predivs = ARRAY_SIZE(clk_out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .reg = 0x1f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .hw.init = CLK_HW_INIT_PARENTS("out-b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &hosc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &pll_core_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &pll_ve_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &pll_ve_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) &pll_ddr_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &pll_ddr_other_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &pll_periph_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &pll_periph_sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &axi_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &ahb_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &ahb_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &apb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &ahb_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &ahb_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &ahb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &ahb_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &ahb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &ahb_ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &ahb_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &ahb_bist_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &ahb_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &ahb_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &ahb_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) &ahb_mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &ahb_ms_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &ahb_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &ahb_sdram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &ahb_ace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &ahb_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &ahb_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) &ahb_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &ahb_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &ahb_spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) &ahb_spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &ahb_pata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &ahb_sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &ahb_gps_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) &ahb_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &ahb_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &ahb_tvd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &ahb_tve0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &ahb_tve1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &ahb_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &ahb_lcd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &ahb_csi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &ahb_csi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &ahb_hdmi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) &ahb_hdmi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) &ahb_de_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &ahb_de_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &ahb_de_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &ahb_de_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &ahb_gmac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &ahb_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &ahb_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &apb0_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &apb0_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &apb0_ac97_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) &apb0_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &apb0_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) &apb0_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) &apb0_ir0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &apb0_ir1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) &apb0_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) &apb0_keypad_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &apb1_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &apb1_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &apb1_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) &apb1_i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) &apb1_can_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) &apb1_scr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) &apb1_ps20_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) &apb1_ps21_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &apb1_i2c4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) &apb1_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &apb1_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &apb1_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) &apb1_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) &apb1_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &apb1_uart5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) &apb1_uart6_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &apb1_uart7_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &ms_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) &mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &mmc3_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) &mmc3_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) &ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) &pata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) &ir0_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) &ir1_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) &ir0_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) &ir1_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) &ac97_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) &keypad_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) &sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) &usb_phy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) &spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) &dram_csi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) &dram_csi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) &dram_tvd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) &dram_tve0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) &dram_tve1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) &dram_out_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) &dram_de_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) &dram_de_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) &dram_de_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) &dram_de_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) &dram_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) &dram_ace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) &de_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) &de_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) &de_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &de_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) &de_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) &tcon0_ch0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) &tcon1_ch0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) &tvd_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) &tvd_sclk1_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) &tvd_sclk2_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) &tcon0_ch1_sclk2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) &tcon0_ch1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) &tcon1_ch1_sclk2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) &tcon1_ch1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &csi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) &csi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) &codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) &ace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) &gpu_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) &gpu_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) &mbus_sun4i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) &mbus_sun7i_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) &hdmi1_slow_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) &hdmi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) &out_a_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) &out_b_clk.common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* Post-divider for pll-audio is hardcoded to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [CLK_HOSC] = &hosc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [CLK_PLL_CORE] = &pll_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [CLK_AXI_DRAM] = &axi_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [CLK_AHB] = &ahb_sun4i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [CLK_APB0] = &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [CLK_MS] = &ms_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [CLK_MMC3] = &mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [CLK_PATA] = &pata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [CLK_IR0] = &ir0_sun4i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [CLK_IR1] = &ir1_sun4i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [CLK_AC97] = &ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [CLK_KEYPAD] = &keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [CLK_SATA] = &sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [CLK_USB_PHY] = &usb_phy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* CLK_GPS is unimplemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [CLK_SPI3] = &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) [CLK_DE_BE0] = &de_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) [CLK_DE_BE1] = &de_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) [CLK_DE_FE0] = &de_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [CLK_DE_FE1] = &de_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [CLK_DE_MP] = &de_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) [CLK_TVD] = &tvd_sun4i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [CLK_CSI0] = &csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) [CLK_CSI1] = &csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [CLK_ACE] = &ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [CLK_GPU] = &gpu_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [CLK_MBUS] = &mbus_sun4i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .num = CLK_NUMBER_SUN4I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) [CLK_HOSC] = &hosc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) [CLK_PLL_CORE] = &pll_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) [CLK_PLL_VE] = &pll_ve_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) [CLK_AHB] = &ahb_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) [CLK_APB0] = &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) [CLK_AHB_HDMI1] = &ahb_hdmi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) [CLK_AHB_GMAC] = &ahb_gmac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) [CLK_APB0_I2S1] = &apb0_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) [CLK_APB0_I2S2] = &apb0_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) [CLK_APB1_I2C3] = &apb1_i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) [CLK_APB1_I2C4] = &apb1_i2c4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) [CLK_MS] = &ms_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) [CLK_MMC3] = &mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) [CLK_PATA] = &pata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) [CLK_IR0] = &ir0_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) [CLK_IR1] = &ir1_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) [CLK_AC97] = &ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) [CLK_KEYPAD] = &keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) [CLK_SATA] = &sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) [CLK_USB_PHY] = &usb_phy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* CLK_GPS is unimplemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) [CLK_SPI3] = &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) [CLK_DE_BE0] = &de_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) [CLK_DE_BE1] = &de_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) [CLK_DE_FE0] = &de_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) [CLK_DE_FE1] = &de_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) [CLK_DE_MP] = &de_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) [CLK_TVD_SCLK2] = &tvd_sclk2_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) [CLK_TVD] = &tvd_sclk1_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) [CLK_CSI0] = &csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) [CLK_CSI1] = &csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) [CLK_ACE] = &ace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) [CLK_GPU] = &gpu_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) [CLK_MBUS] = &mbus_sun7i_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) [CLK_HDMI1_SLOW] = &hdmi1_slow_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) [CLK_HDMI1] = &hdmi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) [CLK_OUT_A] = &out_a_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) [CLK_OUT_B] = &out_b_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .num = CLK_NUMBER_SUN7I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) [RST_USB_PHY2] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) [RST_GPS] = { 0x0d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) [RST_DE_BE0] = { 0x104, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) [RST_DE_BE1] = { 0x108, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) [RST_DE_FE0] = { 0x10c, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) [RST_DE_FE1] = { 0x110, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) [RST_DE_MP] = { 0x114, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) [RST_TVE0] = { 0x118, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) [RST_TCON0] = { 0x118, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) [RST_TVE1] = { 0x11c, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) [RST_TCON1] = { 0x11c, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) [RST_CSI0] = { 0x134, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) [RST_CSI1] = { 0x138, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) [RST_VE] = { 0x13c, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) [RST_ACE] = { 0x148, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) [RST_LVDS] = { 0x14c, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) [RST_GPU] = { 0x154, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) [RST_HDMI_H] = { 0x170, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) [RST_HDMI_SYS] = { 0x170, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .ccu_clks = sun4i_sun7i_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .hw_clks = &sun4i_a10_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .resets = sunxi_a10_a20_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .ccu_clks = sun4i_sun7i_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .hw_clks = &sun7i_a20_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .resets = sunxi_a10_a20_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static void __init sun4i_ccu_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) const struct sunxi_ccu_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pr_err("%s: Could not map the clock registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) val = readl(reg + SUN4I_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * Force VCO and PLL bias current to lowest setting. Higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * settings interfere with sigma-delta modulation and result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * in audible noise and distortions when using SPDIF or I2S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) val &= ~GENMASK(25, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) val &= ~GENMASK(29, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * Use the peripheral PLL6 as the AHB parent, instead of CPU /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * AXI which have rate changes due to cpufreq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * This is especially a big deal for the HS timer whose parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * clock is AHB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * NB! These bits are undocumented in A10 manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) val = readl(reg + SUN4I_AHB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) val &= ~GENMASK(7, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) writel(val | (2 << 6), reg + SUN4I_AHB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) sunxi_ccu_probe(node, reg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static void __init sun4i_a10_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) sun4i_a10_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static void __init sun7i_a20_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) sun7i_a20_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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