Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) File  : Clock H/w specific Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Author: Pankaj Dev <pankaj.dev@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Copyright (C) 2014 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __CLKGEN_INFO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __CLKGEN_INFO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern spinlock_t clkgen_a9_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct clkgen_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static inline unsigned long clkgen_read(void __iomem	*base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 					  struct clkgen_field *field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	return (readl(base + field->offset) >> field->shift) & field->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline void clkgen_write(void __iomem *base, struct clkgen_field *field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 				  unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	writel((readl(base + field->offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	       ~(field->mask << field->shift)) | (val << field->shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	       base + field->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLKGEN_FIELD(_offset, _mask, _shift) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				.offset	= _offset,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				.mask	= _mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 				.shift	= _shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		&pll->data->field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		&pll->data->field, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /*__CLKGEN_INFO_H*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)