^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Stephen Gallimore <stephen.gallimore@st.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Pankaj Dev <pankaj.dev@st.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clkgen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_SPINLOCK(clkgen_a9_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * PLL configuration register bits for PLL3200 C32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define C32_NDIV_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define C32_IDF_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define C32_ODF_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define C32_LDF_MASK (0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define C32_CP_MASK (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define C32_MAX_ODFS (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * PLL configuration register bits for PLL4600 C28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define C28_NDIV_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define C28_IDF_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define C28_ODF_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clkgen_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clkgen_field pdn_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clkgen_field pdn_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clkgen_field locked_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clkgen_field mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clkgen_field ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clkgen_field pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clkgen_field idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clkgen_field ldf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clkgen_field cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int num_odfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clkgen_field odf[C32_MAX_ODFS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clkgen_field odf_gate[C32_MAX_ODFS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool switch2pll_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clkgen_field switch2pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct clk_ops stm_pll3200c32_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct clk_ops stm_pll3200c32_a9_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct clk_ops stm_pll4600c28_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 407 C0 PLL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .num_odfs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .ops = &stm_pll3200c32_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* 407 C0 PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .pdn_ctrl = CLKGEN_FIELD(0x2c8, 0x1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_odfs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .ops = &stm_pll3200c32_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* 407 A9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .num_odfs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .switch2pll_en = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .lock = &clkgen_a9_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ops = &stm_pll3200c32_a9_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct clkgen_pll_data st_pll4600c28_418_a9 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 418 A9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .num_odfs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .switch2pll_en = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .lock = &clkgen_a9_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ops = &stm_pll4600c28_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * DOC: Clock Generated by PLL, rate set and enabled by bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * prepare - clk_(un)prepare only ensures parent is (un)prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * enable - clk_enable/disable only ensures parent is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * rate - rate is fixed. No clk_set_rate support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * PLL clock that is integrated in the ClockGenA instances on the STiH415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * and STiH416.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @hw: handle between common and hardware-specific interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @type: PLL instance type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @regs_base: base of the PLL configuration register(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clkgen_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clkgen_pll_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *regs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 odf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct stm_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long odf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long ldf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int clkgen_pll_is_locked(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 locked = CLKGEN_READ(pll, locked_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return !!locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int clkgen_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 poweroff = CLKGEN_READ(pll, pdn_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return !poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int __clkgen_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void __iomem *base = pll->regs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clkgen_field *field = &pll->data->locked_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (clkgen_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CLKGEN_WRITE(pll, pdn_ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = readl_relaxed_poll_timeout(base + field->offset, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) !!((reg >> field->shift) & field->mask), 0, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (pll->data->switch2pll_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLKGEN_WRITE(pll, switch2pll, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int clkgen_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = __clkgen_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void __clkgen_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!clkgen_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (pll->data->switch2pll_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CLKGEN_WRITE(pll, switch2pll, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CLKGEN_WRITE(pll, pdn_ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void clkgen_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __clkgen_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct stm_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long deviation = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long new_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) long new_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Charge pump table: highest ndiv value for cp=6 to 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const unsigned char cp_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 128, 136, 144, 152, 160, 168, 176, 184, 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Output clock range: 800Mhz to 1600Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (output < 800000000 || output > 1600000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) input /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) output /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for (i = 1; i <= 7 && deviation; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) n = i * output / (2 * input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (n < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (n > 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) new_freq = (input * 2 * n) / i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) new_deviation = abs(new_freq - output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!new_deviation || new_deviation < deviation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pll->idf = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pll->ndiv = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) deviation = new_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (deviation == ~0) /* No solution found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Computing recommended charge pump value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!pll->idf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pll->idf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long ndiv, idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned long rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ndiv = CLKGEN_READ(pll, ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) idf = CLKGEN_READ(pll, idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (idf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Note: input is divided to avoid overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static long round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct stm_pll params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!clk_pll3200c32_get_params(*prate, rate, ¶ms))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) clk_pll3200c32_get_rate(*prate, ¶ms, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pr_debug("%s: %s rate %ld Invalid\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __clk_get_name(hw->clk), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) __func__, __clk_get_name(hw->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rate, (unsigned int)params.ndiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (unsigned int)params.idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct stm_pll params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) long hwrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!rate || !parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!clk_pll3200c32_get_params(parent_rate, rate, ¶ms))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) clk_pll3200c32_get_rate(parent_rate, ¶ms, &hwrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __func__, __clk_get_name(hw->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hwrate, (unsigned int)params.ndiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (unsigned int)params.idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!hwrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pll->ndiv = params.ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pll->idf = params.idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pll->cp = params.cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __clkgen_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CLKGEN_WRITE(pll, ndiv, pll->ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CLKGEN_WRITE(pll, idf, pll->idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CLKGEN_WRITE(pll, cp, pll->cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __clkgen_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* PLL output structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * FVCO >> /2 >> FVCOBY2 (no output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * |> Divider (ODF) >> PHI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * 4Mhz <= INFF input <= 350Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * 1 <= i (register/dec value for IDF) <= 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * 8 <= n (register/dec value for NDIV) <= 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct stm_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long i, infin, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned long deviation = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long new_freq, new_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Output clock range: 19Mhz to 3000Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (output < 19000000 || output > 3000000000u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* For better jitter, IDF should be smallest and NDIV must be maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for (i = 1; i <= 7 && deviation; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* INFIN checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) infin = input / i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (infin < 4000000 || infin > 50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) continue; /* Invalid case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) n = output / (infin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (n < 8 || n > 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) continue; /* Invalid case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (n < 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) n++; /* To work around 'y' when n=x.y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (; n >= 8 && deviation; n--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) new_freq = infin * 2 * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (new_freq < output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break; /* Optimization: shorting loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) new_deviation = new_freq - output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!new_deviation || new_deviation < deviation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pll->idf = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pll->ndiv = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) deviation = new_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (deviation == ~0) /* No solution found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned long *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!pll->idf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pll->idf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *rate = (input / pll->idf) * 2 * pll->ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct stm_pll params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) params.ndiv = CLKGEN_READ(pll, ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) params.idf = CLKGEN_READ(pll, idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk_pll4600c28_get_rate(parent_rate, ¶ms, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static long round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct stm_pll params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!clk_pll4600c28_get_params(*prate, rate, ¶ms)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clk_pll4600c28_get_rate(*prate, ¶ms, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pr_debug("%s: %s rate %ld Invalid\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __clk_get_name(hw->clk), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __func__, __clk_get_name(hw->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rate, (unsigned int)params.ndiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (unsigned int)params.idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct clkgen_pll *pll = to_clkgen_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct stm_pll params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) long hwrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!rate || !parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!clk_pll4600c28_get_params(parent_rate, rate, ¶ms)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clk_pll4600c28_get_rate(parent_rate, ¶ms, &hwrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pr_debug("%s: %s rate %ld Invalid\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __clk_get_name(hw->clk), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) __func__, __clk_get_name(hw->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hwrate, (unsigned int)params.ndiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) (unsigned int)params.idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!hwrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pll->ndiv = params.ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pll->idf = params.idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __clkgen_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) CLKGEN_WRITE(pll, ndiv, pll->ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CLKGEN_WRITE(pll, idf, pll->idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) __clkgen_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const struct clk_ops stm_pll3200c32_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .enable = clkgen_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .disable = clkgen_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .is_enabled = clkgen_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .recalc_rate = recalc_stm_pll3200c32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct clk_ops stm_pll3200c32_a9_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .enable = clkgen_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .disable = clkgen_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .is_enabled = clkgen_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .recalc_rate = recalc_stm_pll3200c32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .round_rate = round_rate_stm_pll3200c32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .set_rate = set_rate_stm_pll3200c32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct clk_ops stm_pll4600c28_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .enable = clkgen_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .disable = clkgen_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .is_enabled = clkgen_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .recalc_rate = recalc_stm_pll4600c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .round_rate = round_rate_stm_pll4600c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .set_rate = set_rate_stm_pll4600c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static struct clk * __init clkgen_pll_register(const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct clkgen_pll_data *pll_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) void __iomem *reg, unsigned long pll_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const char *clk_name, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct clkgen_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) init.ops = pll_data->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) init.flags = pll_flags | CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pll->data = pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pll->regs_base = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pll->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) clk = clk_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pr_debug("%s: parent %s rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) __clk_get_name(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) __clk_get_name(clk_get_parent(clk)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void __iomem * __init clkgen_get_register_base(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct device_node *pnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void __iomem *reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pnode = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!pnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) reg = of_iomap(pnode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) of_node_put(pnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct clk * __init clkgen_odf_register(const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct clkgen_pll_data *pll_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned long pll_flags, int odf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spinlock_t *odf_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const char *odf_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct clk_divider *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) gate->flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gate->reg = reg + pll_data->odf_gate[odf].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) gate->bit_idx = pll_data->odf_gate[odf].shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) gate->lock = odf_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) div->reg = reg + pll_data->odf[odf].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) div->shift = pll_data->odf[odf].shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) div->width = fls(pll_data->odf[odf].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) div->lock = odf_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) &div->hw, &clk_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) &gate->hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pr_debug("%s: parent %s rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __clk_get_name(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __clk_get_name(clk_get_parent(clk)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void __init clkgen_c32_pll_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct clkgen_pll_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) const char *parent_name, *pll_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void __iomem *pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int num_odfs, odf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned long pll_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pll_base = clkgen_get_register_base(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) of_clk_detect_critical(np, 0, &pll_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) np->name, data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pll_name = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) num_odfs = data->num_odfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) clk_data->clk_num = num_odfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (!clk_data->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) for (odf = 0; odf < num_odfs; odf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned long odf_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) odf, &clk_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) of_clk_detect_critical(np, odf, &odf_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) odf, &clkgena_c32_odf_lock, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clk_data->clks[odf] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) kfree(pll_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) kfree(clk_data->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void __init clkgen_c32_pll0_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) clkgen_c32_pll_setup(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) (struct clkgen_pll_data *) &st_pll3200c32_cx_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void __init clkgen_c32_pll1_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) clkgen_c32_pll_setup(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (struct clkgen_pll_data *) &st_pll3200c32_cx_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void __init clkgen_c32_plla9_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) clkgen_c32_pll_setup(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) (struct clkgen_pll_data *) &st_pll3200c32_407_a9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void __init clkgen_c28_plla9_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) clkgen_c32_pll_setup(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) (struct clkgen_pll_data *) &st_pll4600c28_418_a9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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