^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clkgen-mux.c: ST GEN-MUX Clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Stephen Gallimore <stephen.gallimore@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Pankaj Dev <pankaj.dev@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clkgen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const char ** __init clkgen_mux_get_parents(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int *num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) const char **parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int nparents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) nparents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (WARN_ON(!nparents))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (!parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *num_parents = of_clk_parent_fill(np, parents, nparents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clkgen_mux_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long clk_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct clkgen_mux_data stih407_a9_mux_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .offset = 0x1a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .lock = &clkgen_a9_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void __init st_of_clkgen_mux_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clkgen_mux_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const char **parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_err("%s: Failed to get base address\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) parents = clkgen_mux_get_parents(np, &num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (IS_ERR(parents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_err("%s: Failed to get parents (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __func__, PTR_ERR(parents));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto err_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk = clk_register_mux(NULL, np->name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) data->clk_flags | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg + data->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) data->shift, data->width, data->mux_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_debug("%s: parent %s rate %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __clk_get_name(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __clk_get_name(clk_get_parent(clk)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (unsigned int)clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) kfree(parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) kfree(parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err_parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void __init st_of_clkgen_a9_mux_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) st_of_clkgen_mux_setup(np, &stih407_a9_mux_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) st_of_clkgen_a9_mux_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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