^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clk-flexgen.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) ST-Microelectronics SA 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clkgen_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) bool mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct flexgen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Crossbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Pre-divisor's gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk_gate pgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Pre-divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_divider pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Final divisor's gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_gate fgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Final divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk_divider fdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Asynchronous mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_gate sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* hw control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool control_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int flexgen_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_hw *pgate_hw = &flexgen->pgate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_hw *fgate_hw = &flexgen->fgate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __clk_hw_set_clk(pgate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __clk_hw_set_clk(fgate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clk_gate_ops.enable(pgate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk_gate_ops.enable(fgate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void flexgen_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk_hw *fgate_hw = &flexgen->fgate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* disable only the final gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __clk_hw_set_clk(fgate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_gate_ops.disable(fgate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int flexgen_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk_hw *fgate_hw = &flexgen->fgate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __clk_hw_set_clk(fgate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!clk_gate_ops.is_enabled(fgate_hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static u8 flexgen_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_hw *mux_hw = &flexgen->mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return clk_mux_ops.get_parent(mux_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int flexgen_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_hw *mux_hw = &flexgen->mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return clk_mux_ops.set_parent(mux_hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk_best_div(unsigned long parent_rate, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Round div according to exact prate and wished rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) div = clk_best_div(*prate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *prate = rate * div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return *prate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static unsigned long flexgen_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long mid_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __clk_hw_set_clk(pdiv_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __clk_hw_set_clk(fdiv_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct flexgen *flexgen = to_flexgen(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk_hw *sync_hw = &flexgen->sync.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct clk_gate *config = to_clk_gate(sync_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __clk_hw_set_clk(pdiv_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __clk_hw_set_clk(fdiv_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (flexgen->control_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg = readl(config->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) reg &= ~BIT(config->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(reg, config->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) div = clk_best_div(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * pdiv is mainly targeted for low freq results, while fdiv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * should be used for div <= 64. The other way round can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * lead to 'duty cycle' issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (div <= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct clk_ops flexgen_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .enable = flexgen_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .disable = flexgen_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .is_enabled = flexgen_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .get_parent = flexgen_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .set_parent = flexgen_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .round_rate = flexgen_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .recalc_rate = flexgen_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .set_rate = flexgen_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct clk *clk_register_flexgen(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const char **parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void __iomem *reg, spinlock_t *lock, u32 idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long flexgen_flags, bool mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct flexgen *fgxbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 xbar_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void __iomem *xbar_reg, *fdiv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!fgxbar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) init.ops = &flexgen_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) init.flags = CLK_GET_RATE_NOCACHE | flexgen_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) xbar_reg = reg + 0x18 + (idx & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) xbar_shift = (idx % 4) * 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) fdiv_reg = reg + 0x164 + idx * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Crossbar element config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) fgxbar->mux.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) fgxbar->mux.mask = BIT(6) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) fgxbar->mux.reg = xbar_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) fgxbar->mux.shift = xbar_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) fgxbar->mux.table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Pre-divider's gate config (in xbar register)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) fgxbar->pgate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) fgxbar->pgate.reg = xbar_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fgxbar->pgate.bit_idx = xbar_shift + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Pre-divider config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) fgxbar->pdiv.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) fgxbar->pdiv.width = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Final divider's gate config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) fgxbar->fgate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) fgxbar->fgate.reg = fdiv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fgxbar->fgate.bit_idx = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Final divider config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) fgxbar->fdiv.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) fgxbar->fdiv.reg = fdiv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) fgxbar->fdiv.width = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Final divider sync config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) fgxbar->sync.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) fgxbar->sync.reg = fdiv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) fgxbar->sync.bit_idx = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) fgxbar->control_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) fgxbar->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk = clk_register(NULL, &fgxbar->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) kfree(fgxbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_debug("%s: parent %s rate %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __clk_get_name(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __clk_get_name(clk_get_parent(clk)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (unsigned int)clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char ** __init flexgen_get_parents(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int *num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) const char **parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int nparents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) nparents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (WARN_ON(!nparents))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *num_parents = of_clk_parent_fill(np, parents, nparents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct clkgen_data clkgen_audio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct clkgen_data clkgen_video = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct of_device_id flexgen_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .compatible = "st,flexgen-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .data = &clkgen_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .compatible = "st,flexgen-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .data = &clkgen_video,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void __init st_of_flexgen_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct device_node *pnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const char **parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int num_parents, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spinlock_t *rlock = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct clkgen_data *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long flex_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bool clk_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pnode = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!pnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg = of_iomap(pnode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) of_node_put(pnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) parents = flexgen_get_parents(np, &num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) match = of_match_node(flexgen_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data = (struct clkgen_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) flex_flags = data->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk_mode = data->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pr_err("%s: Failed to get number of output clocks (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __func__, clk_data->clk_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_data->clk_num = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!clk_data->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!rlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_lock_init(rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < clk_data->clk_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i, &clk_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) flex_flags &= ~CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) of_clk_detect_critical(np, i, &flex_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * If we read an empty clock name then the output is unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (*clk_name == '\0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk = clk_register_flexgen(clk_name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) reg, rlock, i, flex_flags, clk_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) clk_data->clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) kfree(parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) kfree(clk_data->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) kfree(parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) kfree(rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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