^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Spreatrum SC9860 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/sprd,sc9860-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "composite.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 6, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 13, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 26, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 104, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 4, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 25, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 50, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 10, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 32, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate", "ext-26m", 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate", "ext-26m", 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static SPRD_SC_GATE_CLK(ltepll0_gate, "ltepll0-gate", "ext-26m", 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate", "ext-26m", 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static SPRD_SC_GATE_CLK(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate", "ext-26m", 0x16c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x1000, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate", "ext-26m", 0x16c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x1000, BIT(18), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate", "ext-26m", 0x2b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* address base is 0x402b0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &mpll0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &mpll1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &dpll0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &dpll1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) <epll0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) &twpll_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <epll1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &rpll0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) &rpll1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &cppll_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &gpll_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clk_hw_onecell_data sc9860_pmu_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [CLK_FAC_4M] = &fac_4m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [CLK_FAC_2M] = &fac_2m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [CLK_FAC_1M] = &fac_1m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [CLK_FAC_250K] = &fac_250k.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [CLK_FAC_RCO25M] = &fac_rco_25m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [CLK_FAC_RCO4M] = &fac_rco_4m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [CLK_FAC_RCO2M] = &fac_rco_2m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [CLK_FAC_3K2] = &fac_3k2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [CLK_FAC_1K] = &fac_1k.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [CLK_MPLL0_GATE] = &mpll0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [CLK_MPLL1_GATE] = &mpll1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [CLK_DPLL0_GATE] = &dpll0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [CLK_DPLL1_GATE] = &dpll1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [CLK_LTEPLL0_GATE] = <epll0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [CLK_TWPLL_GATE] = &twpll_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [CLK_LTEPLL1_GATE] = <epll1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [CLK_RPLL0_GATE] = &rpll0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [CLK_RPLL1_GATE] = &rpll1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [CLK_CPPLL_GATE] = &cppll_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [CLK_GPLL_GATE] = &gpll_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .num = CLK_PMU_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct sprd_clk_desc sc9860_pmu_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .clk_clks = sc9860_pmu_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_clk_clks = ARRAY_SIZE(sc9860_pmu_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .hw_clks = &sc9860_pmu_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* GPLL/LPLL/DPLL/RPLL/CPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* TWPLL/MPLL0/MPLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .shift = 20, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .shift = 19, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .shift = 18, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .shift = 17, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .shift = 11, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .shift = 56, .width = 1 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 2, itable2, f_mpll0, 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 1000, 1000, 1, 1300000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .shift = 20, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .shift = 19, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .shift = 18, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .shift = 17, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .shift = 11, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .shift = 56, .width = 1 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .shift = 0, .width = 0 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 2, itable2, f_mpll1, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .shift = 16, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .shift = 15, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .shift = 14, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .shift = 13, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .shift = 8, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .shift = 0, .width = 0 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 2, itable1, f_dpll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 2, itable1, f_dpll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .shift = 0, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .shift = 3, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .shift = 80, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .shift = 81, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .shift = 14, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .shift = 16, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .shift = 4, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .shift = 0, .width = 0 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 3, itable1, f_rpll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 3, itable1, f_rpll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .shift = 21, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .shift = 20, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .shift = 19, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .shift = 18, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .shift = 13, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .shift = 0, .width = 0 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 2, itable2, f_twpll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .shift = 31, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .shift = 27, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .shift = 26, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .shift = 25, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { .shift = 20, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .shift = 0, .width = 0 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x64, 2, itable1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) f_ltepll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x6c, 2, itable1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) f_ltepll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .shift = 18, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .shift = 15, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { .shift = 14, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .shift = 13, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .shift = 8, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .shift = 17, .width = 1 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 2, itable1, f_gpll, 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 1000, 1000, 1, 600000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .shift = 17, .width = 1 }, /* lock_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .shift = 15, .width = 1 }, /* div_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .shift = 14, .width = 1 }, /* mod_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .shift = 13, .width = 1 }, /* sdm_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .shift = 0, .width = 0 }, /* refin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .shift = 8, .width = 2 }, /* ibias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .shift = 0, .width = 7 }, /* n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .shift = 57, .width = 7 }, /* nint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { .shift = 32, .width = 23}, /* kint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { .shift = 0, .width = 0 }, /* prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .shift = 0, .width = 0 }, /* postdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 2, itable1, f_cppll, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct sprd_clk_common *sc9860_pll_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* address base is 0x40400000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) &mpll0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &mpll1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) &dpll0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) &dpll1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) &rpll0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &rpll1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) &twpll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) <epll0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) <epll1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) &gpll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &cppll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct clk_hw_onecell_data sc9860_pll_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [CLK_MPLL0] = &mpll0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [CLK_MPLL1] = &mpll1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [CLK_DPLL0] = &dpll0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [CLK_DPLL1] = &dpll1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [CLK_RPLL0] = &rpll0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [CLK_RPLL1] = &rpll1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [CLK_TWPLL] = &twpll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [CLK_LTEPLL0] = <epll0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [CLK_LTEPLL1] = <epll1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [CLK_GPLL] = &gpll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [CLK_CPPLL] = &cppll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [CLK_GPLL_42M5] = &gpll_42m5.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [CLK_TWPLL_768M] = &twpll_768m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [CLK_TWPLL_384M] = &twpll_384m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [CLK_TWPLL_192M] = &twpll_192m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [CLK_TWPLL_96M] = &twpll_96m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [CLK_TWPLL_48M] = &twpll_48m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [CLK_TWPLL_24M] = &twpll_24m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [CLK_TWPLL_12M] = &twpll_12m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [CLK_TWPLL_512M] = &twpll_512m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [CLK_TWPLL_256M] = &twpll_256m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [CLK_TWPLL_128M] = &twpll_128m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [CLK_TWPLL_64M] = &twpll_64m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [CLK_TWPLL_307M2] = &twpll_307m2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [CLK_TWPLL_153M6] = &twpll_153m6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [CLK_TWPLL_76M8] = &twpll_76m8.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [CLK_TWPLL_51M2] = &twpll_51m2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [CLK_TWPLL_38M4] = &twpll_38m4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [CLK_TWPLL_19M2] = &twpll_19m2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [CLK_L0_614M4] = &l0_614m4.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [CLK_L0_409M6] = &l0_409m6.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [CLK_L0_38M] = &l0_38m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [CLK_L1_38M] = &l1_38m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [CLK_RPLL0_192M] = &rpll0_192m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [CLK_RPLL0_96M] = &rpll0_96m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [CLK_RPLL0_48M] = &rpll0_48m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [CLK_RPLL1_468M] = &rpll1_468m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [CLK_RPLL1_192M] = &rpll1_192m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [CLK_RPLL1_96M] = &rpll1_96m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [CLK_RPLL1_64M] = &rpll1_64m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [CLK_RPLL1_48M] = &rpll1_48m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [CLK_DPLL0_50M] = &dpll0_50m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [CLK_DPLL1_50M] = &dpll1_50m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [CLK_CPPLL_50M] = &cppll_50m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [CLK_M0_39M] = &m0_39m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [CLK_M1_63M] = &m1_63m.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num = CLK_PLL_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct sprd_clk_desc sc9860_pll_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .clk_clks = sc9860_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .num_clk_clks = ARRAY_SIZE(sc9860_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .hw_clks = &sc9860_pll_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SC9860_MUX_FLAG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "twpll-96m", "twpll-128m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x20, 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x2c, 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const char * const uart_parents[] = { "ext-26m", "twpll-48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "twpll-51m2", "twpll-96m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const char * const i2c_parents[] = { "ext-26m", "twpll-48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "twpll-51m2", "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static SPRD_COMP_CLK(i2c0_clk, "i2c0", i2c_parents, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static SPRD_COMP_CLK(i2c1_clk, "i2c1", i2c_parents, 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static SPRD_COMP_CLK(i2c2_clk, "i2c2", i2c_parents, 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static SPRD_COMP_CLK(i2c3_clk, "i2c3", i2c_parents, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static SPRD_COMP_CLK(i2c4_clk, "i2c4", i2c_parents, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static SPRD_COMP_CLK(i2c5_clk, "i2c5", i2c_parents, 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const char * const spi_parents[] = { "ext-26m", "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "twpll-153m6", "twpll-192m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const char * const iis_parents[] = { "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static SPRD_COMP_CLK(iis0_clk, "iis0", iis_parents, 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0, 2, 8, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static SPRD_COMP_CLK(iis1_clk, "iis1", iis_parents, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0, 2, 8, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static SPRD_COMP_CLK(iis2_clk, "iis2", iis_parents, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0, 2, 8, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static SPRD_COMP_CLK(iis3_clk, "iis3", iis_parents, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0, 2, 8, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct sprd_clk_common *sc9860_ap_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* address base is 0x20000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &ap_apb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &ap_usb3.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &i2c4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &i2c5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &iis0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &iis1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &iis2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &iis3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_hw_onecell_data sc9860_ap_clk_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [CLK_AP_APB] = &ap_apb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [CLK_AP_USB3] = &ap_usb3.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [CLK_UART0] = &uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [CLK_UART1] = &uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [CLK_UART2] = &uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [CLK_UART3] = &uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [CLK_UART4] = &uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) [CLK_I2C0] = &i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [CLK_I2C1] = &i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [CLK_I2C2] = &i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [CLK_I2C3] = &i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [CLK_I2C4] = &i2c4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [CLK_I2C5] = &i2c5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [CLK_SPI3] = &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [CLK_IIS0] = &iis0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [CLK_IIS1] = &iis1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [CLK_IIS2] = &iis2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [CLK_IIS3] = &iis3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .num = CLK_AP_CLK_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct sprd_clk_desc sc9860_ap_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .clk_clks = sc9860_ap_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .num_clk_clks = ARRAY_SIZE(sc9860_ap_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .hw_clks = &sc9860_ap_clk_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const char * const aon_apb_parents[] = { "rco-25m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "ext-rco-100m", "twpll-96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0, 3, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const char * const aux_parents[] = { "ext-32k", "rpll0-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "rpll1-26m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "cppll-50m", "rco-25m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "dpll0-50m", "dpll1-50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "gpll-42m5", "twpll-48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "m0-39m", "m1-63m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "l0-38m", "l1-38m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static SPRD_COMP_CLK(aux0_clk, "aux0", aux_parents, 0x238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0, 5, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static SPRD_COMP_CLK(aux1_clk, "aux1", aux_parents, 0x23c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0, 5, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static SPRD_COMP_CLK(aux2_clk, "aux2", aux_parents, 0x240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0, 5, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static SPRD_COMP_CLK(probe_clk, "probe", aux_parents, 0x244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0, 5, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const char * const sp_ahb_parents[] = { "rco-4m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "ext-rco-100m", "twpll-96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0, 3, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const char * const cci_parents[] = { "ext-26m", "twpll-384m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "l0-614m4", "twpll-768m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static SPRD_COMP_CLK(cci_clk, "cci", cci_parents, 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0, 2, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static SPRD_COMP_CLK(gic_clk, "gic", cci_parents, 0x304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0, 2, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static SPRD_COMP_CLK(cssys_clk, "cssys", cci_parents, 0x310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0, 2, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const char * const sdio_2x_parents[] = { "fac-1m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "twpll-307m2", "twpll-384m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) "l0-409m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static SPRD_COMP_CLK(sdio0_2x, "sdio0-2x", sdio_2x_parents, 0x328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0, 3, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static SPRD_COMP_CLK(sdio1_2x, "sdio1-2x", sdio_2x_parents, 0x330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0, 3, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static SPRD_COMP_CLK(sdio2_2x, "sdio2-2x", sdio_2x_parents, 0x338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0, 3, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static SPRD_COMP_CLK(emmc_2x, "emmc-2x", sdio_2x_parents, 0x340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0, 3, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static SPRD_DIV_CLK(sdio0_1x, "sdio0-1x", "sdio0-2x", 0x32c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 8, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static SPRD_DIV_CLK(sdio1_1x, "sdio1-1x", "sdio1-2x", 0x334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 8, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static SPRD_DIV_CLK(sdio2_1x, "sdio2-1x", "sdio2-2x", 0x33c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 8, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static SPRD_DIV_CLK(emmc_1x, "emmc-1x", "emmc-2x", 0x344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 8, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const char * const adi_parents[] = { "rco-4m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "rco-25m", "twpll-38m4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "twpll-51m2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static SPRD_MUX_CLK(adi_clk, "adi", adi_parents, 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const char * const pwm_parents[] = { "ext-32k", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "rco-4m", "rco-25m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "twpll-48m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const char * const efuse_parents[] = { "rco-25m", "ext-26m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const char * const cm3_uart_parents[] = { "rco-4m", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "rco-100m", "twpll-48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "twpll-51m2", "twpll-96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "twpll-128m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const char * const thm_parents[] = { "ext-32k", "fac-250k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static SPRD_MUX_CLK(thm_clk, "thm", thm_parents, 0x270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const char * const cm3_i2c_parents[] = { "rco-4m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "rco-100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "twpll-48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "twpll-51m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const char * const cm4_spi_parents[] = { "ext-26m", "twpll-96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "rco-100m", "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "twpll-153m6", "twpll-192m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "rco-100m", "twpll-76m8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "twpll-128m", "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0, 3, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "clk-twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "clk-twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const char * const debounce_parents[] = { "ext-32k", "rco-4m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "rco-25m", "ext-26m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "twpll-48m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "twpll-128m", "twpll-256m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct sprd_clk_common *sc9860_aon_prediv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* address base is 0x402d0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) &aon_apb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &aux0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) &aux1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &aux2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &probe_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &sp_ahb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &cci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) &gic_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &cssys_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) &sdio0_2x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &sdio1_2x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &sdio2_2x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) &emmc_2x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &sdio0_1x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &sdio1_1x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) &sdio2_1x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) &emmc_1x.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &adi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &pwm0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) &pwm1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &pwm2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &pwm3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) &efuse_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) &cm3_uart0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &cm3_uart1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) &thm_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &cm3_i2c0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) &cm3_i2c1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &cm4_spi.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &aon_i2c.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &ca53_dap.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &ca53_ts.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &djtag_tck.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &pmu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &pmu_26m.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &debounce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &otg2_ref.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &usb3_ref.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) &ap_axi.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct clk_hw_onecell_data sc9860_aon_prediv_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [CLK_AON_APB] = &aon_apb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [CLK_AUX0] = &aux0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [CLK_AUX1] = &aux1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [CLK_AUX2] = &aux2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [CLK_PROBE] = &probe_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [CLK_SP_AHB] = &sp_ahb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [CLK_CCI] = &cci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [CLK_GIC] = &gic_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [CLK_CSSYS] = &cssys_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [CLK_SDIO0_2X] = &sdio0_2x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [CLK_SDIO1_2X] = &sdio1_2x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [CLK_SDIO2_2X] = &sdio2_2x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [CLK_EMMC_2X] = &emmc_2x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [CLK_SDIO0_1X] = &sdio0_1x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [CLK_SDIO1_1X] = &sdio1_1x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [CLK_SDIO2_1X] = &sdio2_1x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [CLK_EMMC_1X] = &emmc_1x.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [CLK_ADI] = &adi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [CLK_PWM0] = &pwm0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [CLK_PWM1] = &pwm1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [CLK_PWM2] = &pwm2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [CLK_PWM3] = &pwm3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [CLK_EFUSE] = &efuse_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [CLK_CM3_UART0] = &cm3_uart0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [CLK_CM3_UART1] = &cm3_uart1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [CLK_THM] = &thm_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [CLK_CM3_I2C0] = &cm3_i2c0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [CLK_CM3_I2C1] = &cm3_i2c1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [CLK_CM4_SPI] = &cm4_spi.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [CLK_AON_I2C] = &aon_i2c.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [CLK_CA53_DAP] = &ca53_dap.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [CLK_CA53_TS] = &ca53_ts.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [CLK_DJTAG_TCK] = &djtag_tck.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [CLK_PMU] = &pmu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [CLK_PMU_26M] = &pmu_26m.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [CLK_DEBOUNCE] = &debounce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [CLK_OTG2_REF] = &otg2_ref.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [CLK_USB3_REF] = &usb3_ref.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [CLK_AP_AXI] = &ap_axi.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .num = CLK_AON_PREDIV_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct sprd_clk_desc sc9860_aon_prediv_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .clk_clks = sc9860_aon_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .num_clk_clks = ARRAY_SIZE(sc9860_aon_prediv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .hw_clks = &sc9860_aon_prediv_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static SPRD_SC_GATE_CLK(usb3_eb, "usb3-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static SPRD_SC_GATE_CLK(usb3_suspend, "usb3-suspend", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static SPRD_SC_GATE_CLK(usb3_ref_eb, "usb3-ref-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static SPRD_SC_GATE_CLK(dma_eb, "dma-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static SPRD_SC_GATE_CLK(sdio0_eb, "sdio0-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static SPRD_SC_GATE_CLK(sdio1_eb, "sdio1-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static SPRD_SC_GATE_CLK(sdio2_eb, "sdio2-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static SPRD_SC_GATE_CLK(emmc_eb, "emmc-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static SPRD_SC_GATE_CLK(rom_eb, "rom-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static SPRD_SC_GATE_CLK(busmon_eb, "busmon-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static SPRD_SC_GATE_CLK(cc63s_eb, "cc63s-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static SPRD_SC_GATE_CLK(cc63p_eb, "cc63p-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static SPRD_SC_GATE_CLK(ce0_eb, "ce0-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static SPRD_SC_GATE_CLK(ce1_eb, "ce1-eb", "ap-axi", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct sprd_clk_common *sc9860_apahb_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* address base is 0x20210000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) &usb3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) &usb3_suspend.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &usb3_ref_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) &dma_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) &sdio0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) &sdio1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) &sdio2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) &emmc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) &rom_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) &busmon_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) &cc63s_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) &cc63p_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &ce0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) &ce1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static struct clk_hw_onecell_data sc9860_apahb_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [CLK_USB3_EB] = &usb3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [CLK_USB3_SUSPEND_EB] = &usb3_suspend.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [CLK_USB3_REF_EB] = &usb3_ref_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [CLK_DMA_EB] = &dma_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [CLK_SDIO0_EB] = &sdio0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [CLK_SDIO1_EB] = &sdio1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [CLK_SDIO2_EB] = &sdio2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [CLK_EMMC_EB] = &emmc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [CLK_ROM_EB] = &rom_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [CLK_BUSMON_EB] = &busmon_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [CLK_CC63S_EB] = &cc63s_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [CLK_CC63P_EB] = &cc63p_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [CLK_CE0_EB] = &ce0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [CLK_CE1_EB] = &ce1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .num = CLK_APAHB_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct sprd_clk_desc sc9860_apahb_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .clk_clks = sc9860_apahb_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .num_clk_clks = ARRAY_SIZE(sc9860_apahb_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .hw_clks = &sc9860_apahb_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static SPRD_SC_GATE_CLK(kpd_eb, "kpd-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static SPRD_SC_GATE_CLK(ap_sys_eb, "ap-sys-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static SPRD_SC_GATE_CLK(efuse_eb, "efuse-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static SPRD_SC_GATE_CLK(pub1_reg_eb, "pub1-reg-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static SPRD_SC_GATE_CLK(adi_eb, "adi-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static SPRD_SC_GATE_CLK(ap_intc0_eb, "ap-intc0-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static SPRD_SC_GATE_CLK(ap_intc1_eb, "ap-intc1-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static SPRD_SC_GATE_CLK(ap_intc2_eb, "ap-intc2-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static SPRD_SC_GATE_CLK(ap_intc3_eb, "ap-intc3-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static SPRD_SC_GATE_CLK(ap_intc4_eb, "ap-intc4-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static SPRD_SC_GATE_CLK(splk_eb, "splk-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static SPRD_SC_GATE_CLK(mspi_eb, "mspi-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static SPRD_SC_GATE_CLK(pub0_reg_eb, "pub0-reg-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static SPRD_SC_GATE_CLK(pin_eb, "pin-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static SPRD_SC_GATE_CLK(gpu_eb, "gpu-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static SPRD_SC_GATE_CLK(apcpu_ts0_eb, "apcpu-ts0-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static SPRD_SC_GATE_CLK(apcpu_ts1_eb, "apcpu-ts1-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static SPRD_SC_GATE_CLK(dap_eb, "dap-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static SPRD_SC_GATE_CLK(i2c_eb, "i2c-eb", "aon-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static SPRD_SC_GATE_CLK(pmu_eb, "pmu-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static SPRD_SC_GATE_CLK(thm_eb, "thm-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static SPRD_SC_GATE_CLK(aux0_eb, "aux0-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static SPRD_SC_GATE_CLK(aux1_eb, "aux1-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static SPRD_SC_GATE_CLK(aux2_eb, "aux2-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static SPRD_SC_GATE_CLK(probe_eb, "probe-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static SPRD_SC_GATE_CLK(gpu0_avs_eb, "gpu0-avs-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static SPRD_SC_GATE_CLK(gpu1_avs_eb, "gpu1-avs-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static SPRD_SC_GATE_CLK(apcpu_wdg_eb, "apcpu-wdg-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static SPRD_SC_GATE_CLK(disp_emc_eb, "disp-emc-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static SPRD_SC_GATE_CLK(lvds_trx_eb, "lvds-trx-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static SPRD_SC_GATE_CLK(lvds_tcxo_eb, "lvds-tcxo-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static SPRD_SC_GATE_CLK(mdar_eb, "mdar-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static SPRD_SC_GATE_CLK(djtag_eb, "djtag-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static SPRD_SC_GATE_CLK(mbox_eb, "mbox-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static SPRD_SC_GATE_CLK(def_eb, "def-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static SPRD_SC_GATE_CLK(aon_apb_rsv0, "aon-apb-rsv0", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static SPRD_SC_GATE_CLK(orp_jtag_eb, "orp-jtag-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static SPRD_SC_GATE_CLK(vsp_eb, "vsp-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static SPRD_SC_GATE_CLK(cam_eb, "cam-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static SPRD_SC_GATE_CLK(disp_eb, "disp-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static SPRD_SC_GATE_CLK(sdio0_2x_en, "sdio0-2x-en", "aon-apb", 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) 0x1000, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static SPRD_SC_GATE_CLK(sdio1_2x_en, "sdio1-2x-en", "aon-apb", 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) 0x1000, BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) 0x1000, BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) 0x1000, BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb", "aon-apb", 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static struct sprd_clk_common *sc9860_aon_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* address base is 0x402e0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &avs_lit_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) &avs_big_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) &ap_intc5_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) &gpio_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) &pwm0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) &pwm1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) &pwm2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) &pwm3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) &kpd_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) &aon_sys_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) &ap_sys_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) &aon_tmr_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &ap_tmr0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) &efuse_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) &eic_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) &pub1_reg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) &adi_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) &ap_intc0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) &ap_intc1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) &ap_intc2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) &ap_intc3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) &ap_intc4_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) &splk_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) &mspi_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) &pub0_reg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) &pin_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) &aon_ckg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) &gpu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) &apcpu_ts0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) &apcpu_ts1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) &dap_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) &i2c_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) &pmu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) &thm_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) &aux0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) &aux1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) &aux2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) &probe_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) &gpu0_avs_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) &gpu1_avs_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) &apcpu_wdg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) &ap_tmr1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) &ap_tmr2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) &disp_emc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) &zip_emc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) &gsp_emc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) &osc_aon_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) &lvds_trx_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) &lvds_tcxo_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) &mdar_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) &rtc4m0_cal_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) &rct100m_cal_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) &djtag_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) &mbox_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) &aon_dma_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) &dbg_emc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) &lvds_pll_div_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) &def_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) &aon_apb_rsv0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) &orp_jtag_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) &vsp_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) &cam_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) &disp_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) &dbg_axi_if_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) &sdio0_2x_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) &sdio1_2x_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) &sdio2_2x_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) &emmc_2x_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) &arch_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) &kpb_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) &aon_syst_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) &ap_syst_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) &aon_tmr_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) &ap_tmr0_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) &eic_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) &eic_rtcdv5_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) &ap_wdg_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) &ap_tmr1_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) &ap_tmr2_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) &dcxo_tmr_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) &bb_cal_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) &avs_big_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) &avs_lit_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) &avs_gpu0_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) &avs_gpu1_rtc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) &gpu_ts_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) &rtcdv10_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [CLK_AVS_LIT_EB] = &avs_lit_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [CLK_AVS_BIG_EB] = &avs_big_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [CLK_GPIO_EB] = &gpio_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [CLK_PWM0_EB] = &pwm0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [CLK_PWM1_EB] = &pwm1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [CLK_PWM2_EB] = &pwm2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [CLK_PWM3_EB] = &pwm3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [CLK_KPD_EB] = &kpd_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [CLK_AON_SYS_EB] = &aon_sys_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [CLK_AP_SYS_EB] = &ap_sys_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [CLK_EFUSE_EB] = &efuse_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [CLK_EIC_EB] = &eic_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [CLK_PUB1_REG_EB] = &pub1_reg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [CLK_ADI_EB] = &adi_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [CLK_SPLK_EB] = &splk_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [CLK_MSPI_EB] = &mspi_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [CLK_PUB0_REG_EB] = &pub0_reg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [CLK_PIN_EB] = &pin_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [CLK_AON_CKG_EB] = &aon_ckg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [CLK_GPU_EB] = &gpu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [CLK_APCPU_TS1_EB] = &apcpu_ts1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [CLK_DAP_EB] = &dap_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [CLK_I2C_EB] = &i2c_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [CLK_PMU_EB] = &pmu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [CLK_THM_EB] = &thm_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [CLK_AUX0_EB] = &aux0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [CLK_AUX1_EB] = &aux1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [CLK_AUX2_EB] = &aux2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [CLK_PROBE_EB] = &probe_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [CLK_GPU0_AVS_EB] = &gpu0_avs_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [CLK_GPU1_AVS_EB] = &gpu1_avs_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [CLK_OSC_AON_EB] = &osc_aon_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [CLK_LVDS_TRX_EB] = &lvds_trx_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [CLK_LVDS_TCXO_EB] = &lvds_tcxo_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [CLK_MDAR_EB] = &mdar_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [CLK_RCT100M_CAL_EB] = &rct100m_cal_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [CLK_DJTAG_EB] = &djtag_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [CLK_MBOX_EB] = &mbox_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [CLK_LVDS_PLL_DIV_EN] = &lvds_pll_div_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [CLK_DEF_EB] = &def_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) [CLK_AON_APB_RSV0] = &aon_apb_rsv0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [CLK_ORP_JTAG_EB] = &orp_jtag_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [CLK_VSP_EB] = &vsp_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [CLK_CAM_EB] = &cam_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [CLK_DISP_EB] = &disp_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [CLK_KPB_RTC_EB] = &kpb_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [CLK_DCXO_TMR_RTC_EB] = &dcxo_tmr_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [CLK_AVS_BIG_RTC_EB] = &avs_big_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [CLK_AVS_LIT_RTC_EB] = &avs_lit_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [CLK_AVS_GPU0_RTC_EB] = &avs_gpu0_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [CLK_AVS_GPU1_RTC_EB] = &avs_gpu1_rtc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [CLK_GPU_TS_EB] = &gpu_ts_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [CLK_RTCDV10_EB] = &rtcdv10_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .num = CLK_AON_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const struct sprd_clk_desc sc9860_aon_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .clk_clks = sc9860_aon_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .num_clk_clks = ARRAY_SIZE(sc9860_aon_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .hw_clks = &sc9860_aon_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static const char * const lit_mcu_parents[] = { "ext-26m", "twpll-512m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) "twpll-768m", "ltepll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "twpll", "mpll0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mcu_table, 0, 4, 4, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const char * const big_mcu_parents[] = { "ext-26m", "twpll-512m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "twpll-768m", "ltepll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "twpll", "mpll1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mcu_table, 0, 4, 4, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static struct sprd_clk_common *sc9860_aonsecure_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* address base is 0x40880000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) &lit_mcu.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) &big_mcu.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) [CLK_LIT_MCU] = &lit_mcu.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) [CLK_BIG_MCU] = &big_mcu.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .num = CLK_AONSECURE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .clk_clks = sc9860_aonsecure_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .num_clk_clks = ARRAY_SIZE(sc9860_aonsecure_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .hw_clks = &sc9860_aonsecure_clk_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static SPRD_SC_GATE_CLK(agcp_iis0_eb, "agcp-iis0-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) 0x0, 0x100, BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static SPRD_SC_GATE_CLK(agcp_iis1_eb, "agcp-iis1-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) 0x0, 0x100, BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static SPRD_SC_GATE_CLK(agcp_iis2_eb, "agcp-iis2-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) 0x0, 0x100, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static SPRD_SC_GATE_CLK(agcp_iis3_eb, "agcp-iis3-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) 0x0, 0x100, BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static SPRD_SC_GATE_CLK(agcp_uart_eb, "agcp-uart-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) 0x0, 0x100, BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static SPRD_SC_GATE_CLK(agcp_dmacp_eb, "agcp-dmacp-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) 0x0, 0x100, BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static SPRD_SC_GATE_CLK(agcp_dmaap_eb, "agcp-dmaap-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) 0x0, 0x100, BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) 0x0, 0x100, BIT(10), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) 0x0, 0x100, BIT(11), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static SPRD_SC_GATE_CLK(agcp_mcdt_eb, "agcp-mcdt-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) 0x0, 0x100, BIT(12), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 0x0, 0x100, BIT(13), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static SPRD_SC_GATE_CLK(agcp_vbc_eb, "agcp-vbc-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) 0x0, 0x100, BIT(14), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) 0x0, 0x100, BIT(15), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static SPRD_SC_GATE_CLK(agcp_icu_eb, "agcp-icu-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 0x0, 0x100, BIT(17), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) 0x0, 0x100, BIT(18), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static SPRD_SC_GATE_CLK(agcp_aud_eb, "agcp-aud-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 0x0, 0x100, BIT(19), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static SPRD_SC_GATE_CLK(agcp_audif_eb, "agcp-audif-eb", "aon-apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) 0x0, 0x100, BIT(20), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static struct sprd_clk_common *sc9860_agcp_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* address base is 0x415e0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) &agcp_iis0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &agcp_iis1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) &agcp_iis2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &agcp_iis3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) &agcp_uart_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) &agcp_dmacp_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) &agcp_dmaap_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) &agcp_arc48k_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) &agcp_src44p1k_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &agcp_mcdt_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) &agcp_vbcifd_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &agcp_vbc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &agcp_spinlock_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &agcp_icu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) &agcp_ap_ashb_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) &agcp_cp_ashb_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) &agcp_aud_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &agcp_audif_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static struct clk_hw_onecell_data sc9860_agcp_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) [CLK_AGCP_IIS0_EB] = &agcp_iis0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) [CLK_AGCP_IIS1_EB] = &agcp_iis1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) [CLK_AGCP_IIS2_EB] = &agcp_iis2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) [CLK_AGCP_IIS3_EB] = &agcp_iis3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) [CLK_AGCP_UART_EB] = &agcp_uart_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) [CLK_AGCP_ARC48K_EB] = &agcp_arc48k_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) [CLK_AGCP_SRC44P1K_EB] = &agcp_src44p1k_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) [CLK_AGCP_MCDT_EB] = &agcp_mcdt_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) [CLK_AGCP_VBCIFD_EB] = &agcp_vbcifd_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) [CLK_AGCP_VBC_EB] = &agcp_vbc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) [CLK_AGCP_SPINLOCK_EB] = &agcp_spinlock_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) [CLK_AGCP_ICU_EB] = &agcp_icu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) [CLK_AGCP_AP_ASHB_EB] = &agcp_ap_ashb_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) [CLK_AGCP_CP_ASHB_EB] = &agcp_cp_ashb_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) [CLK_AGCP_AUD_EB] = &agcp_aud_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .num = CLK_AGCP_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const struct sprd_clk_desc sc9860_agcp_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .clk_clks = sc9860_agcp_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .num_clk_clks = ARRAY_SIZE(sc9860_agcp_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .hw_clks = &sc9860_agcp_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const char * const gpu_parents[] = { "twpll-512m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "twpll-768m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static SPRD_COMP_CLK(gpu_clk, "gpu", gpu_parents, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) 0, 2, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static struct sprd_clk_common *sc9860_gpu_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* address base is 0x60200000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static struct clk_hw_onecell_data sc9860_gpu_clk_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .num = CLK_GPU_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const struct sprd_clk_desc sc9860_gpu_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .clk_clks = sc9860_gpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .num_clk_clks = ARRAY_SIZE(sc9860_gpu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .hw_clks = &sc9860_gpu_clk_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const char * const ahb_parents[] = { "ext-26m", "twpll-96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) "twpll-128m", "twpll-153m6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static const char * const vsp_parents[] = { "twpll-76m8", "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) "twpll-256m", "twpll-307m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) "twpll-384m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static const char * const dispc_parents[] = { "twpll-76m8", "twpll-128m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) "twpll-256m", "twpll-307m2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) "twpll-192m", "twpll-256m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static const char * const vsp_26m_parents[] = { "ext-26m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) 0, 1, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static struct sprd_clk_common *sc9860_vsp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* address base is 0x61000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &ahb_vsp.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) &vsp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) &vsp_enc.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) &vpp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &vsp_26m.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static struct clk_hw_onecell_data sc9860_vsp_clk_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) [CLK_AHB_VSP] = &ahb_vsp.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) [CLK_VSP] = &vsp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) [CLK_VSP_ENC] = &vsp_enc.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) [CLK_VPP] = &vpp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) [CLK_VSP_26M] = &vsp_26m.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .num = CLK_VSP_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static const struct sprd_clk_desc sc9860_vsp_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .clk_clks = sc9860_vsp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .num_clk_clks = ARRAY_SIZE(sc9860_vsp_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .hw_clks = &sc9860_vsp_clk_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) 0x1000, BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) 0x1000, BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) 0x1000, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) 0x1000, BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) 0x1000, BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) 0x1000, BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static SPRD_GATE_CLK(vpp_axi_gate, "vpp-axi-gate", "ahb-vsp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static SPRD_GATE_CLK(vsp_bm_gate, "vsp-bm-gate", "ahb-vsp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) BIT(8), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static SPRD_GATE_CLK(vpp_bm_gate, "vpp-bm-gate", "ahb-vsp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) BIT(10), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static struct sprd_clk_common *sc9860_vsp_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* address base is 0x61100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) &vsp_dec_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) &vsp_ckg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) &vsp_mmu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) &vsp_enc_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) &vpp_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) &vsp_26m_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) &vsp_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) &vsp_enc_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) &vpp_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) &vsp_bm_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) &vsp_enc_bm_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) &vpp_bm_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static struct clk_hw_onecell_data sc9860_vsp_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) [CLK_VSP_DEC_EB] = &vsp_dec_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) [CLK_VSP_CKG_EB] = &vsp_ckg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) [CLK_VSP_MMU_EB] = &vsp_mmu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) [CLK_VSP_ENC_EB] = &vsp_enc_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) [CLK_VPP_EB] = &vpp_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) [CLK_VSP_26M_EB] = &vsp_26m_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) [CLK_VSP_AXI_GATE] = &vsp_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) [CLK_VSP_ENC_GATE] = &vsp_enc_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) [CLK_VPP_AXI_GATE] = &vpp_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) [CLK_VSP_BM_GATE] = &vsp_bm_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) [CLK_VSP_ENC_BM_GATE] = &vsp_enc_bm_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) [CLK_VPP_BM_GATE] = &vpp_bm_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .num = CLK_VSP_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static const struct sprd_clk_desc sc9860_vsp_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .clk_clks = sc9860_vsp_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .num_clk_clks = ARRAY_SIZE(sc9860_vsp_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .hw_clks = &sc9860_vsp_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static const char * const sensor_parents[] = { "ext-26m", "twpll-48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) "twpll-76m8", "twpll-96m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) 0, 2, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) BIT(16), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) BIT(16), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static struct sprd_clk_common *sc9860_cam_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* address base is 0x62000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) &ahb_cam.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &sensor0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) &sensor1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) &sensor2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) &mipi_csi0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) &mipi_csi1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static struct clk_hw_onecell_data sc9860_cam_clk_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) [CLK_AHB_CAM] = &ahb_cam.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) [CLK_SENSOR0] = &sensor0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) [CLK_SENSOR1] = &sensor1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) [CLK_SENSOR2] = &sensor2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) [CLK_MIPI_CSI0_EB] = &mipi_csi0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) [CLK_MIPI_CSI1_EB] = &mipi_csi1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .num = CLK_CAM_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static const struct sprd_clk_desc sc9860_cam_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .clk_clks = sc9860_cam_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .num_clk_clks = ARRAY_SIZE(sc9860_cam_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .hw_clks = &sc9860_cam_clk_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static SPRD_SC_GATE_CLK(dcam0_eb, "dcam0-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) 0x1000, BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static SPRD_SC_GATE_CLK(dcam1_eb, "dcam1-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) 0x1000, BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static SPRD_SC_GATE_CLK(isp0_eb, "isp0-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) 0x1000, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static SPRD_SC_GATE_CLK(csi0_eb, "csi0-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) 0x1000, BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static SPRD_SC_GATE_CLK(csi1_eb, "csi1-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) 0x1000, BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static SPRD_SC_GATE_CLK(jpg0_eb, "jpg0-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) 0x1000, BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static SPRD_SC_GATE_CLK(jpg1_eb, "jpg1-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) 0x1000, BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) 0x1000, BIT(7), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) 0x1000, BIT(8), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static SPRD_SC_GATE_CLK(isp1_eb, "isp1-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) 0x1000, BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static SPRD_SC_GATE_CLK(cpp_eb, "cpp-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) 0x1000, BIT(10), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static SPRD_SC_GATE_CLK(mmu_pf_eb, "mmu-pf-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 0x1000, BIT(11), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static SPRD_SC_GATE_CLK(isp2_eb, "isp2-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) 0x1000, BIT(12), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) 0x1000, BIT(13), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) 0x1000, BIT(14), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static SPRD_SC_GATE_CLK(isp_lclk_eb, "isp-lclk-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) 0x1000, BIT(15), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static SPRD_SC_GATE_CLK(isp_iclk_eb, "isp-iclk-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) 0x1000, BIT(16), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static SPRD_SC_GATE_CLK(isp_mclk_eb, "isp-mclk-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) 0x1000, BIT(17), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static SPRD_SC_GATE_CLK(isp_pclk_eb, "isp-pclk-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) 0x1000, BIT(18), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) 0x1000, BIT(19), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static SPRD_SC_GATE_CLK(dcam0_if_eb, "dcam0-if-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) 0x1000, BIT(20), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static SPRD_SC_GATE_CLK(clk26m_if_eb, "clk26m-if-eb", "ahb-cam", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) 0x1000, BIT(21), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static SPRD_GATE_CLK(cphy1_gate, "cphy1-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static SPRD_GATE_CLK(mipi_csi1, "mipi-csi1", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static SPRD_GATE_CLK(dcam0_axi_gate, "dcam0-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static SPRD_GATE_CLK(dcam1_axi_gate, "dcam1-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static SPRD_GATE_CLK(sensor0_gate, "sensor0-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static SPRD_GATE_CLK(sensor1_gate, "sensor1-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) BIT(7), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) BIT(8), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) BIT(10), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) BIT(11), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) BIT(12), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static SPRD_GATE_CLK(cpp_axi_gate, "cpp-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) BIT(13), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static SPRD_GATE_CLK(d0_if_axi_gate, "d0-if-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) BIT(14), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) BIT(15), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) BIT(16), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) BIT(17), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate", "ahb-cam", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) BIT(18), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) 0x1000, BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) 0x1000, BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) 0x1000, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) 0x1000, BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) 0x1000, BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static SPRD_SC_GATE_CLK(ib_in_d2i_en, "ib-in-d2i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) 0x1000, BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static SPRD_SC_GATE_CLK(ic_in_d2i_en, "ic-in-d2i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) 0x1000, BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) 0x1000, BIT(7), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) 0x1000, BIT(8), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en", "ahb-cam", 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) 0x1000, BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static struct sprd_clk_common *sc9860_cam_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* address base is 0x62100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) &dcam0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) &dcam1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) &isp0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) &csi0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) &csi1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) &jpg0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) &jpg1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) &cam_ckg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) &cam_mmu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) &isp1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) &cpp_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) &mmu_pf_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) &isp2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) &dcam2isp_if_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) &isp2dcam_if_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) &isp_lclk_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) &isp_iclk_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) &isp_mclk_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) &isp_pclk_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) &isp_isp2dcam_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) &dcam0_if_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) &clk26m_if_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) &cphy0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) &mipi_csi0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) &cphy1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) &mipi_csi1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) &dcam0_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) &dcam1_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) &sensor0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) &sensor1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) &jpg0_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) &gpg1_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) &isp0_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) &isp1_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) &isp2_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) &cpp_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) &d0_if_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) &d2i_if_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) &i2d_if_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) &spare_axi_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) &sensor2_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) &d0if_in_d_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) &d1if_in_d_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) &d0if_in_d2i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) &d1if_in_d2i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) &ia_in_d2i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &ib_in_d2i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) &ic_in_d2i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) &ia_in_i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) &ib_in_i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) &ic_in_i_en.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct clk_hw_onecell_data sc9860_cam_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) [CLK_DCAM0_EB] = &dcam0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) [CLK_DCAM1_EB] = &dcam1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) [CLK_ISP0_EB] = &isp0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) [CLK_CSI0_EB] = &csi0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) [CLK_CSI1_EB] = &csi1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) [CLK_JPG0_EB] = &jpg0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) [CLK_JPG1_EB] = &jpg1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) [CLK_CAM_CKG_EB] = &cam_ckg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) [CLK_CAM_MMU_EB] = &cam_mmu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) [CLK_ISP1_EB] = &isp1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) [CLK_CPP_EB] = &cpp_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) [CLK_MMU_PF_EB] = &mmu_pf_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) [CLK_ISP2_EB] = &isp2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) [CLK_DCAM2ISP_IF_EB] = &dcam2isp_if_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) [CLK_ISP2DCAM_IF_EB] = &isp2dcam_if_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) [CLK_ISP_LCLK_EB] = &isp_lclk_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) [CLK_ISP_ICLK_EB] = &isp_iclk_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) [CLK_ISP_MCLK_EB] = &isp_mclk_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) [CLK_ISP_PCLK_EB] = &isp_pclk_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) [CLK_ISP_ISP2DCAM_EB] = &isp_isp2dcam_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) [CLK_DCAM0_IF_EB] = &dcam0_if_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) [CLK_CLK26M_IF_EB] = &clk26m_if_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) [CLK_CPHY0_GATE] = &cphy0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) [CLK_MIPI_CSI0_GATE] = &mipi_csi0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) [CLK_CPHY1_GATE] = &cphy1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) [CLK_MIPI_CSI1] = &mipi_csi1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) [CLK_DCAM0_AXI_GATE] = &dcam0_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) [CLK_DCAM1_AXI_GATE] = &dcam1_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) [CLK_SENSOR0_GATE] = &sensor0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) [CLK_SENSOR1_GATE] = &sensor1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) [CLK_CPP_AXI_GATE] = &cpp_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) [CLK_D0_IF_AXI_GATE] = &d0_if_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) [CLK_D2I_IF_AXI_GATE] = &d2i_if_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) [CLK_I2D_IF_AXI_GATE] = &i2d_if_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) [CLK_SPARE_AXI_GATE] = &spare_axi_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) [CLK_SENSOR2_GATE] = &sensor2_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) [CLK_D0IF_IN_D_EN] = &d0if_in_d_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) [CLK_D1IF_IN_D_EN] = &d1if_in_d_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) [CLK_D0IF_IN_D2I_EN] = &d0if_in_d2i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) [CLK_D1IF_IN_D2I_EN] = &d1if_in_d2i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) [CLK_IA_IN_D2I_EN] = &ia_in_d2i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) [CLK_IB_IN_D2I_EN] = &ib_in_d2i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) [CLK_IC_IN_D2I_EN] = &ic_in_d2i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) [CLK_IA_IN_I_EN] = &ia_in_i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) [CLK_IB_IN_I_EN] = &ib_in_i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) [CLK_IC_IN_I_EN] = &ic_in_i_en.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .num = CLK_CAM_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static const struct sprd_clk_desc sc9860_cam_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .clk_clks = sc9860_cam_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .num_clk_clks = ARRAY_SIZE(sc9860_cam_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .hw_clks = &sc9860_cam_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) 0, 2, SC9860_MUX_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents, 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) 0, 2, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) 0, 2, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static struct sprd_clk_common *sc9860_disp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* address base is 0x63000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) &ahb_disp.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) &dispc0_dpi.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) &dispc1_dpi.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static struct clk_hw_onecell_data sc9860_disp_clk_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) [CLK_AHB_DISP] = &ahb_disp.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) [CLK_DISPC0_DPI] = &dispc0_dpi.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) [CLK_DISPC1_DPI] = &dispc1_dpi.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .num = CLK_DISP_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static const struct sprd_clk_desc sc9860_disp_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .clk_clks = sc9860_disp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .num_clk_clks = ARRAY_SIZE(sc9860_disp_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .hw_clks = &sc9860_disp_clk_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static SPRD_SC_GATE_CLK(dispc0_eb, "dispc0-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) 0x1000, BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static SPRD_SC_GATE_CLK(dispc1_eb, "dispc1-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) 0x1000, BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static SPRD_SC_GATE_CLK(dispc_mmu_eb, "dispc-mmu-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) 0x1000, BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static SPRD_SC_GATE_CLK(gsp0_eb, "gsp0-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) 0x1000, BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static SPRD_SC_GATE_CLK(gsp1_eb, "gsp1-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) 0x1000, BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static SPRD_SC_GATE_CLK(gsp0_mmu_eb, "gsp0-mmu-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) 0x1000, BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static SPRD_SC_GATE_CLK(gsp1_mmu_eb, "gsp1-mmu-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) 0x1000, BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static SPRD_SC_GATE_CLK(dsi0_eb, "dsi0-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) 0x1000, BIT(7), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static SPRD_SC_GATE_CLK(dsi1_eb, "dsi1-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) 0x1000, BIT(8), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static SPRD_SC_GATE_CLK(disp_ckg_eb, "disp-ckg-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) 0x1000, BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static SPRD_SC_GATE_CLK(disp_gpu_eb, "disp-gpu-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) 0x1000, BIT(10), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) 0x1000, BIT(13), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) 0x1000, BIT(14), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) 0x1000, BIT(15), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static SPRD_SC_GATE_CLK(dispc_mtx_eb, "dispc-mtx-eb", "ahb-disp", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) 0x1000, BIT(16), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static SPRD_GATE_CLK(dphy0_gate, "dphy0-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) BIT(0), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static SPRD_GATE_CLK(dphy1_gate, "dphy1-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) BIT(1), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static SPRD_GATE_CLK(gsp0_a_gate, "gsp0-a-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) BIT(2), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static SPRD_GATE_CLK(gsp1_a_gate, "gsp1-a-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) BIT(3), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static SPRD_GATE_CLK(gsp0_f_gate, "gsp0-f-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) BIT(4), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static SPRD_GATE_CLK(gsp1_f_gate, "gsp1-f-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) BIT(5), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static SPRD_GATE_CLK(d_mtx_f_gate, "d-mtx-f-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) BIT(6), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static SPRD_GATE_CLK(d_mtx_a_gate, "d-mtx-a-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) BIT(7), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static SPRD_GATE_CLK(d_noc_f_gate, "d-noc-f-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) BIT(8), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static SPRD_GATE_CLK(d_noc_a_gate, "d-noc-a-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) BIT(9), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) BIT(10), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) BIT(11), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) BIT(12), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) BIT(13), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) BIT(14), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp", 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) BIT(15), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static struct sprd_clk_common *sc9860_disp_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* address base is 0x63100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) &dispc0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) &dispc1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) &dispc_mmu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) &gsp0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) &gsp1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) &gsp0_mmu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) &gsp1_mmu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) &dsi0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) &dsi1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) &disp_ckg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) &disp_gpu_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) &gpu_mtx_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) &gsp_mtx_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) &tmc_mtx_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) &dispc_mtx_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) &dphy0_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) &dphy1_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) &gsp0_a_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) &gsp1_a_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) &gsp0_f_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) &gsp1_f_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) &d_mtx_f_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) &d_mtx_a_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) &d_noc_f_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) &d_noc_a_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) &gsp_mtx_f_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) &gsp_mtx_a_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) &gsp_noc_f_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) &gsp_noc_a_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) &dispm0idle_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) &gspm0idle_gate.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static struct clk_hw_onecell_data sc9860_disp_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) [CLK_DISPC0_EB] = &dispc0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) [CLK_DISPC1_EB] = &dispc1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) [CLK_DISPC_MMU_EB] = &dispc_mmu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) [CLK_GSP0_EB] = &gsp0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) [CLK_GSP1_EB] = &gsp1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) [CLK_GSP0_MMU_EB] = &gsp0_mmu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) [CLK_GSP1_MMU_EB] = &gsp1_mmu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) [CLK_DSI0_EB] = &dsi0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) [CLK_DSI1_EB] = &dsi1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) [CLK_DISP_CKG_EB] = &disp_ckg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) [CLK_DISP_GPU_EB] = &disp_gpu_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) [CLK_GPU_MTX_EB] = &gpu_mtx_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) [CLK_GSP_MTX_EB] = &gsp_mtx_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) [CLK_TMC_MTX_EB] = &tmc_mtx_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) [CLK_DISPC_MTX_EB] = &dispc_mtx_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) [CLK_DPHY0_GATE] = &dphy0_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) [CLK_DPHY1_GATE] = &dphy1_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) [CLK_GSP0_A_GATE] = &gsp0_a_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) [CLK_GSP1_A_GATE] = &gsp1_a_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) [CLK_GSP0_F_GATE] = &gsp0_f_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) [CLK_GSP1_F_GATE] = &gsp1_f_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) [CLK_D_MTX_F_GATE] = &d_mtx_f_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) [CLK_D_MTX_A_GATE] = &d_mtx_a_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) [CLK_D_NOC_F_GATE] = &d_noc_f_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) [CLK_D_NOC_A_GATE] = &d_noc_a_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) [CLK_GSP_MTX_F_GATE] = &gsp_mtx_f_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) [CLK_GSP_MTX_A_GATE] = &gsp_mtx_a_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) [CLK_GSP_NOC_F_GATE] = &gsp_noc_f_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) [CLK_GSP_NOC_A_GATE] = &gsp_noc_a_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) [CLK_DISPM0IDLE_GATE] = &dispm0idle_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) [CLK_GSPM0IDLE_GATE] = &gspm0idle_gate.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .num = CLK_DISP_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static const struct sprd_clk_desc sc9860_disp_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .clk_clks = sc9860_disp_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .num_clk_clks = ARRAY_SIZE(sc9860_disp_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .hw_clks = &sc9860_disp_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static SPRD_SC_GATE_CLK(sim0_eb, "sim0-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static SPRD_SC_GATE_CLK(iis0_eb, "iis0-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static SPRD_SC_GATE_CLK(iis1_eb, "iis1-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static SPRD_SC_GATE_CLK(iis2_eb, "iis2-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) static SPRD_SC_GATE_CLK(iis3_eb, "iis3-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static SPRD_SC_GATE_CLK(spi0_eb, "spi0-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static SPRD_SC_GATE_CLK(spi1_eb, "spi1-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static SPRD_SC_GATE_CLK(spi2_eb, "spi2-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static SPRD_SC_GATE_CLK(i2c0_eb, "i2c0-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static SPRD_SC_GATE_CLK(i2c1_eb, "i2c1-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static SPRD_SC_GATE_CLK(i2c2_eb, "i2c2-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static SPRD_SC_GATE_CLK(i2c3_eb, "i2c3-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static SPRD_SC_GATE_CLK(i2c4_eb, "i2c4-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static SPRD_SC_GATE_CLK(i2c5_eb, "i2c5-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static SPRD_SC_GATE_CLK(uart0_eb, "uart0-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static SPRD_SC_GATE_CLK(uart1_eb, "uart1-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static SPRD_SC_GATE_CLK(uart2_eb, "uart2-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static SPRD_SC_GATE_CLK(uart3_eb, "uart3-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static SPRD_SC_GATE_CLK(uart4_eb, "uart4-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static SPRD_SC_GATE_CLK(ap_ckg_eb, "ap-ckg-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static SPRD_SC_GATE_CLK(spi3_eb, "spi3-eb", "ap-apb", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static struct sprd_clk_common *sc9860_apapb_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* address base is 0x70b00000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) &sim0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) &iis0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) &iis1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) &iis2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) &iis3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) &spi0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) &spi1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) &spi2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) &i2c0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) &i2c1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) &i2c2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) &i2c3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) &i2c4_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) &i2c5_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) &uart0_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) &uart1_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) &uart2_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) &uart3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) &uart4_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) &ap_ckg_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) &spi3_eb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static struct clk_hw_onecell_data sc9860_apapb_gate_hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) [CLK_SIM0_EB] = &sim0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) [CLK_IIS0_EB] = &iis0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) [CLK_IIS1_EB] = &iis1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) [CLK_IIS2_EB] = &iis2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) [CLK_IIS3_EB] = &iis3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) [CLK_SPI0_EB] = &spi0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) [CLK_SPI1_EB] = &spi1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) [CLK_SPI2_EB] = &spi2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) [CLK_I2C0_EB] = &i2c0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) [CLK_I2C1_EB] = &i2c1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) [CLK_I2C2_EB] = &i2c2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) [CLK_I2C3_EB] = &i2c3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) [CLK_I2C4_EB] = &i2c4_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) [CLK_I2C5_EB] = &i2c5_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) [CLK_UART0_EB] = &uart0_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) [CLK_UART1_EB] = &uart1_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) [CLK_UART2_EB] = &uart2_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) [CLK_UART3_EB] = &uart3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) [CLK_UART4_EB] = &uart4_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) [CLK_AP_CKG_EB] = &ap_ckg_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) [CLK_SPI3_EB] = &spi3_eb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .num = CLK_APAPB_GATE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static const struct sprd_clk_desc sc9860_apapb_gate_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .clk_clks = sc9860_apapb_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .num_clk_clks = ARRAY_SIZE(sc9860_apapb_gate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .hw_clks = &sc9860_apapb_gate_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static const struct of_device_id sprd_sc9860_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) { .compatible = "sprd,sc9860-pmu-gate", /* 0x402b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .data = &sc9860_pmu_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) { .compatible = "sprd,sc9860-pll", /* 0x4040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .data = &sc9860_pll_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) { .compatible = "sprd,sc9860-ap-clk", /* 0x2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .data = &sc9860_ap_clk_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) { .compatible = "sprd,sc9860-aon-prediv", /* 0x402d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .data = &sc9860_aon_prediv_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) { .compatible = "sprd,sc9860-apahb-gate", /* 0x2021 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .data = &sc9860_apahb_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) { .compatible = "sprd,sc9860-aon-gate", /* 0x402e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .data = &sc9860_aon_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) { .compatible = "sprd,sc9860-aonsecure-clk", /* 0x4088 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .data = &sc9860_aonsecure_clk_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) { .compatible = "sprd,sc9860-agcp-gate", /* 0x415e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .data = &sc9860_agcp_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) { .compatible = "sprd,sc9860-gpu-clk", /* 0x6020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .data = &sc9860_gpu_clk_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) { .compatible = "sprd,sc9860-vsp-clk", /* 0x6100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .data = &sc9860_vsp_clk_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) { .compatible = "sprd,sc9860-vsp-gate", /* 0x6110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .data = &sc9860_vsp_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) { .compatible = "sprd,sc9860-cam-clk", /* 0x6200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .data = &sc9860_cam_clk_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) { .compatible = "sprd,sc9860-cam-gate", /* 0x6210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .data = &sc9860_cam_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) { .compatible = "sprd,sc9860-disp-clk", /* 0x6300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .data = &sc9860_disp_clk_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) { .compatible = "sprd,sc9860-disp-gate", /* 0x6310 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .data = &sc9860_disp_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) { .compatible = "sprd,sc9860-apapb-gate", /* 0x70b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .data = &sc9860_apapb_gate_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static int sc9860_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) const struct sprd_clk_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) pr_err("%s: of_match_node() failed", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) desc = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ret = sprd_clk_regmap_init(pdev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) return sprd_clk_probe(&pdev->dev, desc->hw_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static struct platform_driver sc9860_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .probe = sc9860_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .name = "sc9860-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .of_match_table = sprd_sc9860_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) module_platform_driver(sc9860_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) MODULE_ALIAS("platform:sc9860-clk");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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