^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Spreadtrum pll clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2015~2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPRD_PLL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPRD_PLL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct reg_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct clk_bit_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PLL_LOCK_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PLL_DIV_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PLL_MOD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PLL_SDM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PLL_REFIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PLL_IBIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PLL_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PLL_NINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PLL_KINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PLL_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PLL_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PLL_FACT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct sprd_pll - definition of adjustable pll clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @reg: registers used to set the configuration of pll clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * reg[0] shows how many registers this pll clock uses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @itable: pll ibias table, itable[0] means how many items this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * table includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @udelay delay time after setting rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @factors used to calculate the pll clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @fvco: fvco threshold rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @fflag: fvco flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct sprd_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 regs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const u64 *itable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct clk_bit_field *factors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 udelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 k1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 k2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 fflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u64 fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct sprd_clk_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) _regs_num, _itable, _factors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) _udelay, _k1, _k2, _fflag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) _fvco, _fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct sprd_pll _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .regs_num = _regs_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .itable = _itable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .factors = _factors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .udelay = _udelay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .k1 = _k1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .k2 = _k2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .fflag = _fflag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .fvco = _fvco, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .hw.init = _fn(_name, _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) &sprd_pll_ops, 0),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) _regs_num, _itable, _factors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) _udelay, _k1, _k2, _fflag, _fvco) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) _itable, _factors, _udelay, _k1, _k2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) _fflag, _fvco, CLK_HW_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) _regs_num, _itable, _factors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) _udelay, _k1, _k2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) _regs_num, _itable, _factors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) _udelay, _k1, _k2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) _regs_num, _itable, _factors, _udelay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) _regs_num, _itable, _factors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) _udelay, 1000, 1000, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) _itable, _factors, _udelay, _k1, _k2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) _fflag, _fvco) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) _itable, _factors, _udelay, _k1, _k2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) _fflag, _fvco, CLK_HW_INIT_FW_NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) _factors, _udelay, _k1, _k2, _fflag, _fvco) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) _itable, _factors, _udelay, _k1, _k2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) _fflag, _fvco, CLK_HW_INIT_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return container_of(common, struct sprd_pll, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern const struct clk_ops sprd_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif /* _SPRD_PLL_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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