^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Spreadtrum pll clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2015~2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_1M 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_10M (CLK_PLL_1M * 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define pindex(pll, member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define pshift(pll, member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define pwidth(pll, member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) pll->factors[member].width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define pmask(pll, member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ((pwidth(pll, member)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pshift(pll, member)) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define pinternal(pll, cfg, member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (cfg[pindex(pll, member)] & pmask(pll, member))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define pinternal_val(pll, cfg, member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (pinternal(pll, cfg, member) >> pshift(pll, member))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) sprd_pll_read(const struct sprd_pll *pll, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct sprd_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (WARN_ON(index >= pll->regs_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) regmap_read(common->regmap, common->reg + index * 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sprd_pll_write(const struct sprd_pll *pll, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 msk, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct sprd_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int offset, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (WARN_ON(index >= pll->regs_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) offset = common->reg + index * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = regmap_read(common->regmap, offset, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_write(common->regmap, offset, (reg & ~msk) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static unsigned long pll_get_refin(const struct sprd_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 shift, mask, index, refin_id = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const unsigned long refin[4] = { 2, 4, 13, 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (pwidth(pll, PLL_REFIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) index = pindex(pll, PLL_REFIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) shift = pshift(pll, PLL_REFIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mask = pmask(pll, PLL_REFIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) refin_id = (sprd_pll_read(pll, index) & mask) >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (refin_id > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) refin_id = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return refin[refin_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static u32 pll_get_ibias(u64 rate, const u64 *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 i, num = table[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* table[0] indicates the number of items in this table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (rate <= table[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return i == num ? num - 1 : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 i, mask, regs_num = pll->regs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long rate, nint, kint = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u64 refin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 k1, k2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) for (i = 0; i < regs_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cfg[i] = sprd_pll_read(pll, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) refin = pll_get_refin(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (pinternal(pll, cfg, PLL_PREDIV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) refin = refin * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (pwidth(pll, PLL_POSTDIV) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) refin = refin / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!pinternal(pll, cfg, PLL_DIV_S)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) nint = pinternal_val(pll, cfg, PLL_NINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (pinternal(pll, cfg, PLL_SDM_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) kint = pinternal_val(pll, cfg, PLL_KINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mask = pmask(pll, PLL_KINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) k1 = pll->k1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) k2 = pll->k2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ((mask >> __ffs(mask)) + 1)) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) k2 + refin * nint * CLK_PLL_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int _sprd_pll_set_rate(const struct sprd_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct reg_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 mask, shift, width, ibias_val, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 regs_num = pll->regs_num, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long kint, nint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 tmp, refin, fvco = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) refin = pll_get_refin(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mask = pmask(pll, PLL_PREDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) index = pindex(pll, PLL_PREDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) width = pwidth(pll, PLL_PREDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (width && (sprd_pll_read(pll, index) & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) refin = refin * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mask = pmask(pll, PLL_POSTDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) index = pindex(pll, PLL_POSTDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) width = pwidth(pll, PLL_POSTDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cfg[index].msk = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (width && ((pll->fflag == 1 && fvco <= pll->fvco) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (pll->fflag == 0 && fvco > pll->fvco)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cfg[index].val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (width && fvco <= pll->fvco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) fvco = fvco * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mask = pmask(pll, PLL_DIV_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) index = pindex(pll, PLL_DIV_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cfg[index].val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cfg[index].msk |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mask = pmask(pll, PLL_SDM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) index = pindex(pll, PLL_SDM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cfg[index].val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) cfg[index].msk |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) nint = do_div(fvco, refin * CLK_PLL_1M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mask = pmask(pll, PLL_NINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) index = pindex(pll, PLL_NINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) shift = pshift(pll, PLL_NINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cfg[index].val |= (nint << shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cfg[index].msk |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mask = pmask(pll, PLL_KINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) index = pindex(pll, PLL_KINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) width = pwidth(pll, PLL_KINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) shift = pshift(pll, PLL_KINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmp = fvco - refin * nint * CLK_PLL_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmp = do_div(tmp, 10000) * ((mask >> shift) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) kint = DIV_ROUND_CLOSEST_ULL(tmp, refin * 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cfg[index].val |= (kint << shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cfg[index].msk |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ibias_val = pll_get_ibias(fvco, pll->itable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mask = pmask(pll, PLL_IBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) index = pindex(pll, PLL_IBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) shift = pshift(pll, PLL_IBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cfg[index].val |= ibias_val << shift & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cfg[index].msk |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < regs_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (cfg[i].msk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cfg[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) udelay(pll->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static unsigned long sprd_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct sprd_pll *pll = hw_to_sprd_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return _sprd_pll_recalc_rate(pll, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int sprd_pll_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct sprd_pll *pll = hw_to_sprd_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return _sprd_pll_set_rate(pll, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int sprd_pll_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct sprd_pll *pll = hw_to_sprd_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) udelay(pll->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static long sprd_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const struct clk_ops sprd_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .prepare = sprd_pll_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .recalc_rate = sprd_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .round_rate = sprd_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .set_rate = sprd_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) EXPORT_SYMBOL_GPL(sprd_pll_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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