^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Spreadtrum multiplexer clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPRD_MUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPRD_MUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * struct sprd_mux_ssel - Mux clock's source select bits in its register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * @shift: Bit offset of the divider in its register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @width: Width of the divider field in its register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @table: For some mux clocks, not all sources are used on some special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * chips, this matches the value of mux clock's register and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * sources which are used for this mux clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct sprd_mux_ssel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const u8 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct sprd_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct sprd_mux_ssel mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sprd_clk_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define _SPRD_MUX_CLK(_shift, _width, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) _reg, _shift, _width, _flags, _fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct sprd_mux _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .hw.init = _fn(_name, _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &sprd_mux_ops, _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) _reg, _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) _reg, _shift, _width, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CLK_HW_INIT_PARENTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) _reg, _shift, _width, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) _reg, _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) _reg, _shift, _width, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CLK_HW_INIT_PARENTS_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) _reg, _shift, _width, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return container_of(common, struct sprd_mux, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern const struct clk_ops sprd_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct sprd_mux_ssel *mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct sprd_mux_ssel *mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif /* _SPRD_MUX_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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