Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Spreadtrum multiplexer clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) // Copyright (C) 2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			      const struct sprd_mux_ssel *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u8 parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	regmap_read(common->regmap, common->reg, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	parent = reg >> mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	parent &= (1 << mux->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	if (!mux->table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		return parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	num_parents = clk_hw_get_num_parents(&common->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	for (i = 0; i < num_parents - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		if (parent >= mux->table[i] && parent < mux->table[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	return num_parents - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u8 sprd_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct sprd_mux *cm = hw_to_sprd_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	return sprd_mux_helper_get_parent(&cm->common, &cm->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			       const struct sprd_mux_ssel *mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			       u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	if (mux->table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		index = mux->table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	regmap_read(common->regmap, common->reg, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	regmap_write(common->regmap, common->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			  reg | (index << mux->shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	struct sprd_mux *cm = hw_to_sprd_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const struct clk_ops sprd_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	.get_parent = sprd_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	.set_parent = sprd_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	.determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) EXPORT_SYMBOL_GPL(sprd_mux_ops);