^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Spreadtrum divider clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPRD_DIV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPRD_DIV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * struct sprd_div_internal - Internal divider description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * @shift: Bit offset of the divider in its register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @width: Width of the divider field in its register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * That structure represents a single divider, and is meant to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * embedded in other structures representing the various clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * classes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct sprd_div_internal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define _SPRD_DIV_CLK(_shift, _width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct sprd_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sprd_div_internal div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct sprd_clk_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) _shift, _width, _flags, _fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sprd_div _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .div = _SPRD_DIV_CLK(_shift, _width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .hw.init = _fn(_name, _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) &sprd_div_ops, _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) _shift, _width, _flags, CLK_HW_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) _shift, _width, _flags, CLK_HW_INIT_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return container_of(common, struct sprd_div, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) long sprd_div_helper_round_rate(struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct sprd_div_internal *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct sprd_div_internal *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const struct sprd_div_internal *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern const struct clk_ops sprd_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif /* _SPRD_DIV_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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