Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Spreadtrum composite clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) // Copyright (C) 2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _SPRD_COMPOSITE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _SPRD_COMPOSITE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct sprd_comp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct sprd_mux_ssel	mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct sprd_div_internal	div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct sprd_clk_common	common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				 _mshift, _mwidth, _dshift, _dwidth,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 				 _flags, _fn)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct sprd_comp _struct = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		.mux	= _SPRD_MUX_CLK(_mshift, _mwidth, _table),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.div	= _SPRD_DIV_CLK(_dshift, _dwidth),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.common = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			.regmap		= NULL,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			.reg		= _reg,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			.hw.init = _fn(_name, _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 				       &sprd_comp_ops, _flags),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			 }						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			    _mshift, _mwidth, _dshift, _dwidth, _flags)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 				 _mshift, _mwidth, _dshift, _dwidth,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				 _flags, CLK_HW_INIT_PARENTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		      _mwidth, _dshift, _dwidth, _flags)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			    _mshift, _mwidth, _dshift, _dwidth, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				 _mshift, _mwidth, _dshift,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 				 _dwidth, _flags)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 				 _mshift, _mwidth, _dshift, _dwidth,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 				 _flags, CLK_HW_INIT_PARENTS_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			   _mwidth, _dshift, _dwidth, _flags)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg,	NULL,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				 _mshift, _mwidth, _dshift, _dwidth,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				 _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return container_of(common, struct sprd_comp, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern const struct clk_ops sprd_comp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* _SPRD_COMPOSITE_H_ */