Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Spreadtrum composite clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) // Copyright (C) 2017 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "composite.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static long sprd_comp_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 				unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct sprd_comp *cc = hw_to_sprd_comp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	return sprd_div_helper_round_rate(&cc->common, &cc->div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 					 rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 					  unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct sprd_comp *cc = hw_to_sprd_comp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			     unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct sprd_comp *cc = hw_to_sprd_comp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	return sprd_div_helper_set_rate(&cc->common, &cc->div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				       rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static u8 sprd_comp_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct sprd_comp *cc = hw_to_sprd_comp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	return sprd_mux_helper_get_parent(&cc->common, &cc->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int sprd_comp_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	struct sprd_comp *cc = hw_to_sprd_comp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const struct clk_ops sprd_comp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.get_parent	= sprd_comp_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.set_parent	= sprd_comp_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.round_rate	= sprd_comp_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.recalc_rate	= sprd_comp_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.set_rate	= sprd_comp_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) EXPORT_SYMBOL_GPL(sprd_comp_ops);