^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SPEAr6xx machines clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static DEFINE_SPINLOCK(_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL1_CTR (misc_base + 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL1_FRQ (misc_base + 0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL2_CTR (misc_base + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL2_FRQ (misc_base + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_CLK_CFG (misc_base + 0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PLL_CLK_CFG register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCTR_CLK_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCTR_CLK_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CORE_CLK_CFG (misc_base + 0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* CORE CLK CFG register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HCLK_RATIO_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HCLK_RATIO_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCLK_RATIO_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCLK_RATIO_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PERIP_CLK_CFG (misc_base + 0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* PERIP_CLK_CFG register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLCD_CLK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLCD_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UART_CLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UART_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FIRDA_CLK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FIRDA_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPT0_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPT1_CLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPT2_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPT3_CLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPT_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PERIP1_CLK_ENB (misc_base + 0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PERIP1_CLK_ENB register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UART0_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UART1_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SSP0_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SSP1_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JPEG_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FSMC_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FIRDA_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPT2_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPT3_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO2_CLK_ENB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SSP2_CLK_ENB 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADC_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPT1_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RTC_CLK_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO1_CLK_ENB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_CLK_ENB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SMI_CLK_ENB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLCD_CLK_ENB 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GMAC_CLK_ENB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USBD_CLK_ENB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USBH0_CLK_ENB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USBH1_CLK_ENB 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRSC0_CLK_CFG (misc_base + 0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PRSC1_CLK_CFG (misc_base + 0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PRSC2_CLK_CFG (misc_base + 0x04C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLCD_CLK_SYNT (misc_base + 0x05C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FIRDA_CLK_SYNT (misc_base + 0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UART_CLK_SYNT (misc_base + 0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* vco rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct pll_rate_tbl pll_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct aux_rate_tbl aux_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* For PLL1 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* gpt rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct gpt_rate_tbl gpt_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* For pll1 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {.mscale = 1, .nscale = 0}, /* 83 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void __init spear6xx_clk_init(void __iomem *misc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *clk, *clk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_register_clkdev(clk, "osc_32k_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_register_clkdev(clk, "osc_30m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* clock derived from 32 KHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clk_register_clkdev(clk, NULL, "rtc-spear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* clock derived from 30 MHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk_register_clkdev(clk, "pll3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk_register_clkdev(clk, "vco1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_register_clkdev(clk1, "pll1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk_register_clkdev(clk, "vco2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk_register_clkdev(clk1, "pll2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk_register_clkdev(clk, NULL, "fc880000.wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* clock derived from pll1 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_register_clkdev(clk, "cpu_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) HCLK_RATIO_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_register_clkdev(clk, "ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_register_clkdev(clk, "uart_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clk_register_clkdev(clk, "uart_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) UART0_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_register_clkdev(clk, NULL, "d0000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) UART1_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk_register_clkdev(clk, NULL, "d0080000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk_register_clkdev(clk, "firda_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_register_clkdev(clk, "firda_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clk_register_clkdev(clk, NULL, "firda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk_register_clkdev(clk, "clcd_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_register_clkdev(clk, "clcd_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clk_register_clkdev(clk, NULL, "clcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* gpt clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_register_clkdev(clk, NULL, "gpt0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk_register_clkdev(clk, "gpt1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_register_clkdev(clk, NULL, "gpt1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clk_register_clkdev(clk, "gpt2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk_register_clkdev(clk, NULL, "gpt2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_register_clkdev(clk, "gpt3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_register_clkdev(clk, NULL, "gpt3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* clock derived from pll3 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_register_clkdev(clk, NULL, "e1800000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_register_clkdev(clk, NULL, "e1900000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) clk_register_clkdev(clk, NULL, "e2000000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_register_clkdev(clk, NULL, "e2100000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) USBD_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_register_clkdev(clk, NULL, "designware_udc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* clock derived from ahb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clk_register_clkdev(clk, "ahbmult2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clk_register_clkdev(clk, "ddr_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PCLK_RATIO_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_register_clkdev(clk, "apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DMA_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk_register_clkdev(clk, NULL, "fc400000.dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FSMC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk_register_clkdev(clk, NULL, "d1800000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GMAC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_register_clkdev(clk, NULL, "e0800000.ethernet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) I2C_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_register_clkdev(clk, NULL, "d0200000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) JPEG_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk_register_clkdev(clk, NULL, "jpeg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SMI_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clk_register_clkdev(clk, NULL, "fc000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* clock derived from apb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ADC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_register_clkdev(clk, NULL, "d820b000.adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) clk_register_clkdev(clk, NULL, "f0100000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GPIO1_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk_register_clkdev(clk, NULL, "fc980000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) GPIO2_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk_register_clkdev(clk, NULL, "d8100000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SSP0_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clk_register_clkdev(clk, NULL, "ssp-pl022.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SSP1_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clk_register_clkdev(clk, NULL, "ssp-pl022.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SSP2_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clk_register_clkdev(clk, NULL, "ssp-pl022.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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