^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SPEAr3xx machines clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static DEFINE_SPINLOCK(_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL1_CTR (misc_base + 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL1_FRQ (misc_base + 0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL2_CTR (misc_base + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL2_FRQ (misc_base + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_CLK_CFG (misc_base + 0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* PLL_CLK_CFG register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCTR_CLK_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCTR_CLK_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CORE_CLK_CFG (misc_base + 0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* CORE CLK CFG register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GEN_SYNTH2_3_CLK_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GEN_SYNTH2_3_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HCLK_RATIO_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HCLK_RATIO_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCLK_RATIO_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCLK_RATIO_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PERIP_CLK_CFG (misc_base + 0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* PERIP_CLK_CFG register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UART_CLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UART_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FIRDA_CLK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FIRDA_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPT0_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPT1_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPT2_CLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPT_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PERIP1_CLK_ENB (misc_base + 0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* PERIP1_CLK_ENB register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UART_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SSP_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JPEG_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FIRDA_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPT1_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPT2_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADC_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RTC_CLK_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_CLK_ENB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DMA_CLK_ENB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SMI_CLK_ENB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GMAC_CLK_ENB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USBD_CLK_ENB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USBH_CLK_ENB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define C3_CLK_ENB 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RAS_CLK_ENB (misc_base + 0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RAS_AHB_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RAS_PLL1_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RAS_APB_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RAS_32K_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RAS_24M_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RAS_48M_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RAS_PLL2_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RAS_SYNT0_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RAS_SYNT1_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RAS_SYNT2_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RAS_SYNT3_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PRSC0_CLK_CFG (misc_base + 0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PRSC1_CLK_CFG (misc_base + 0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PRSC2_CLK_CFG (misc_base + 0x04C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AMEM_CLK_CFG (misc_base + 0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AMEM_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLCD_CLK_SYNT (misc_base + 0x05C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FIRDA_CLK_SYNT (misc_base + 0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UART_CLK_SYNT (misc_base + 0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GMAC_CLK_SYNT (misc_base + 0x068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GEN0_CLK_SYNT (misc_base + 0x06C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GEN1_CLK_SYNT (misc_base + 0x070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GEN2_CLK_SYNT (misc_base + 0x074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GEN3_CLK_SYNT (misc_base + 0x078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* pll rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct pll_rate_tbl pll_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct aux_rate_tbl aux_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* For PLL1 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* gpt rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct gpt_rate_tbl gpt_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* For pll1 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {.mscale = 1, .nscale = 0}, /* 83 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* clock parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_MACH_SPEAR300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void __init spear300_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_register_clkdev(clk, NULL, "60000000.clcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_register_clkdev(clk, NULL, "94000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_register_clkdev(clk, NULL, "70000000.sdhci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk_register_clkdev(clk, NULL, "a9000000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_register_clkdev(clk, NULL, "a0000000.kbd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline void spear300_clk_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* array of all spear 310 clock lookups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef CONFIG_MACH_SPEAR310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void __init spear310_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk_register_clkdev(clk, "emi", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk_register_clkdev(clk, NULL, "44000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk_register_clkdev(clk, NULL, "tdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clk_register_clkdev(clk, NULL, "b2000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk_register_clkdev(clk, NULL, "b2080000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk_register_clkdev(clk, NULL, "b2100000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk_register_clkdev(clk, NULL, "b2180000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk_register_clkdev(clk, NULL, "b2200000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void spear310_clk_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* array of all spear 320 clock lookups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifdef CONFIG_MACH_SPEAR320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SPEAR320_UARTX_PCLK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SPEAR320_UART2_PCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SPEAR320_UART3_PCLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SPEAR320_UART4_PCLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SPEAR320_UART5_PCLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SPEAR320_UART6_PCLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SPEAR320_RS485_PCLK_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SMII_PCLK_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SMII_PCLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SMII_PCLK_VAL_PAD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SMII_PCLK_VAL_PLL2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SMII_PCLK_VAL_SYNTH0 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SDHCI_PCLK_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SDHCI_PCLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SDHCI_PCLK_VAL_48M 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SDHCI_PCLK_VAL_SYNTH3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define I2S_REF_PCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define I2S_REF_PCLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define I2S_REF_PCLK_SYNTH_VAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define I2S_REF_PCLK_PLL2_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define UART1_PCLK_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define UART1_PCLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SPEAR320_UARTX_PCLK_VAL_APB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "ras_syn0_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void __init spear320_clk_init(void __iomem *soc_config_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct clk *ras_apb_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0, 125000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clk_register_clkdev(clk, "smii_125m_pad", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk_register_clkdev(clk, NULL, "90000000.clcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_register_clkdev(clk, "emi", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) clk_register_clkdev(clk, NULL, "4c000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk_register_clkdev(clk, NULL, "a7000000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_register_clkdev(clk, NULL, "a8000000.pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) clk_register_clkdev(clk, NULL, "a5000000.spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_register_clkdev(clk, NULL, "a6000000.spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_register_clkdev(clk, NULL, "c_can_platform.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk_register_clkdev(clk, NULL, "c_can_platform.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk_register_clkdev(clk, NULL, "a9400000.i2s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ARRAY_SIZE(i2s_ref_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) I2S_REF_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk_register_clkdev(clk, "i2s_ref_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CLK_SET_RATE_PARENT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk_register_clkdev(clk, "i2s_sclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clk_register_clkdev(clk, "hclk", "aa000000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk_register_clkdev(clk, "hclk", "ab000000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk_register_clkdev(clk, NULL, "a9300000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ARRAY_SIZE(sdhci_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clk_register_clkdev(clk, NULL, "70000000.sdhci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clk_register_clkdev(clk, NULL, "smii_pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clk_register_clkdev(clk, NULL, "smii");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk_register_clkdev(clk, NULL, "a3000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Enforce ras_apb_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) clk_set_parent(clk, ras_apb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) clk_register_clkdev(clk, NULL, "a4000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Enforce ras_apb_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_set_parent(clk, ras_apb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_register_clkdev(clk, NULL, "a9100000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_register_clkdev(clk, NULL, "a9200000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk_register_clkdev(clk, NULL, "60000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ARRAY_SIZE(uartx_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) clk_register_clkdev(clk, NULL, "60100000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct clk *clk, *clk1, *ras_apb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) clk_register_clkdev(clk, "osc_32k_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk_register_clkdev(clk, "osc_24m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* clock derived from 32 KHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_register_clkdev(clk, NULL, "fc900000.rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* clock derived from 24 MHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) clk_register_clkdev(clk, "pll3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_register_clkdev(clk, NULL, "fc880000.wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk_register_clkdev(clk, "vco1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) clk_register_clkdev(clk1, "pll1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk_register_clkdev(clk, "vco2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk_register_clkdev(clk1, "pll2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* clock derived from pll1 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk_register_clkdev(clk, "cpu_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) HCLK_RATIO_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_register_clkdev(clk, "ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_register_clkdev(clk, "uart_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ARRAY_SIZE(uart0_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_register_clkdev(clk, "uart0_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clk_register_clkdev(clk, NULL, "d0000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clk_register_clkdev(clk, "firda_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ARRAY_SIZE(firda_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk_register_clkdev(clk, "firda_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clk_register_clkdev(clk, NULL, "firda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* gpt clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ARRAY_SIZE(gpt_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ARRAY_SIZE(gpt0_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk_register_clkdev(clk, NULL, "gpt0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ARRAY_SIZE(gpt_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ARRAY_SIZE(gpt1_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) clk_register_clkdev(clk, "gpt1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk_register_clkdev(clk, NULL, "gpt1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ARRAY_SIZE(gpt_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ARRAY_SIZE(gpt2_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk_register_clkdev(clk, "gpt2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) clk_register_clkdev(clk, NULL, "gpt2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* general synths clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) clk_register_clkdev(clk, "gen0_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_register_clkdev(clk, "gen1_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk_register_clkdev(clk, "gen2_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk_register_clkdev(clk, "gen3_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* clock derived from pll3 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) USBH_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clk_register_clkdev(clk, NULL, "e1800000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk_register_clkdev(clk, NULL, "e1900000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) clk_register_clkdev(clk, NULL, "e2100000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) clk_register_clkdev(clk, "usbh.0_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clk_register_clkdev(clk, "usbh.1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) USBD_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk_register_clkdev(clk, NULL, "e1100000.usbd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* clock derived from ahb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) clk_register_clkdev(clk, "ahbmult2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) clk_register_clkdev(clk, "ddr_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PCLK_RATIO_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) clk_register_clkdev(clk, "apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) AMEM_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) clk_register_clkdev(clk, "amem_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) C3_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) clk_register_clkdev(clk, NULL, "c3_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DMA_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_register_clkdev(clk, NULL, "fc400000.dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GMAC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_register_clkdev(clk, NULL, "e0800000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) I2C_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk_register_clkdev(clk, NULL, "d0180000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) JPEG_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) clk_register_clkdev(clk, NULL, "jpeg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SMI_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) clk_register_clkdev(clk, NULL, "fc000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* clock derived from apb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ADC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) clk_register_clkdev(clk, NULL, "d0080000.adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GPIO_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_register_clkdev(clk, NULL, "fc980000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) SSP_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_register_clkdev(clk, NULL, "d0100000.spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* RAS clk enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) RAS_AHB_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) clk_register_clkdev(clk, "ras_ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RAS_APB_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) clk_register_clkdev(clk, "ras_apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ras_apb_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) clk_register_clkdev(clk, "ras_32k_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) clk_register_clkdev(clk, "ras_24m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) clk_register_clkdev(clk, "ras_pll1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) clk_register_clkdev(clk, "ras_pll2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk_register_clkdev(clk, "ras_pll3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (of_machine_is_compatible("st,spear300"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) spear300_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) else if (of_machine_is_compatible("st,spear310"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spear310_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else if (of_machine_is_compatible("st,spear320"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spear320_clk_init(soc_config_base, ras_apb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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