^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-spear13xx/spear1340_clock.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPEAr1340 machine clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Clock Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPEAR1340_HCLK_SRC_SEL_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPEAR1340_SCLK_SRC_SEL_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* PLL related registers and bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPEAR1340_PLL_CFG (misc_base + 0x210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PLL_CFG bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPEAR1340_GEN_SYNT_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPEAR1340_PLL_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPEAR1340_PLL3_CLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPEAR1340_PLL2_CLK_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPEAR1340_PLL1_CLK_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PERIP_CLK_CFG bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPEAR1340_SPDIF_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPEAR1340_GPT3_CLK_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPEAR1340_GPT2_CLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPEAR1340_GPT_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPEAR1340_GPT1_CLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPEAR1340_GPT0_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPEAR1340_UART_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPEAR1340_UART1_CLK_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPEAR1340_UART0_CLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPEAR1340_CLCD_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPEAR1340_CLCD_CLK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPEAR1340_C3_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPEAR1340_C3_CLK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPEAR1340_GMAC_PHY_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* I2S_CLK_CFG register mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPEAR1340_I2S_SCLK_X_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPEAR1340_I2S_REF_SEL_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPEAR1340_I2S_REF_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPEAR1340_I2S_SRC_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPEAR1340_RTC_CLK_ENB 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPEAR1340_ADC_CLK_ENB 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPEAR1340_C3_CLK_ENB 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPEAR1340_CLCD_CLK_ENB 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPEAR1340_DMA_CLK_ENB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPEAR1340_GPIO1_CLK_ENB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPEAR1340_GPIO0_CLK_ENB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SPEAR1340_GPT1_CLK_ENB 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SPEAR1340_GPT0_CLK_ENB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SPEAR1340_I2S_PLAY_CLK_ENB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SPEAR1340_I2S_REC_CLK_ENB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPEAR1340_I2C0_CLK_ENB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPEAR1340_SSP_CLK_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPEAR1340_UART0_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SPEAR1340_PCIE_SATA_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SPEAR1340_UOC_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SPEAR1340_UHC1_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SPEAR1340_UHC0_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SPEAR1340_GMAC_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SPEAR1340_CFXD_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPEAR1340_SDHCI_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPEAR1340_SMI_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SPEAR1340_FSMC_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SPEAR1340_SYSRAM0_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SPEAR1340_SYSRAM1_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SPEAR1340_SYSROM_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SPEAR1340_BUS_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SPEAR1340_THSENS_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SPEAR1340_ACP_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SPEAR1340_GPT3_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SPEAR1340_GPT2_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SPEAR1340_KBD_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SPEAR1340_CPU_DBG_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SPEAR1340_DDR_CORE_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SPEAR1340_DDR_CTRL_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPEAR1340_PLGPIO_CLK_ENB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SPEAR1340_SPDIF_IN_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SPEAR1340_VIDEO_IN_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SPEAR1340_CAM0_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SPEAR1340_CAM1_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SPEAR1340_CAM2_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SPEAR1340_CAM3_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SPEAR1340_MALI_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SPEAR1340_CEC0_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SPEAR1340_CEC1_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SPEAR1340_PWM_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SPEAR1340_I2C1_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SPEAR1340_UART1_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static DEFINE_SPINLOCK(_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* pll rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct pll_rate_tbl pll_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* PCLK 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* vco-pll4 rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct pll_rate_tbl pll4_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * All below entries generate 166 MHz for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * different values of vco1div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct frac_rate_tbl amba_synth_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {.div = 0x06062}, /* for vco1div2 = 500 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {.div = 0x04000}, /* for vco1div2 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {.div = 0x03031}, /* for vco1div2 = 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Synthesizer Clock derived from vcodiv2. This clock is one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * possible clocks to feed cpu directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * We can program this synthesizer to make cpu run on different clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Following table provides configuration values to let cpu run on 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * 250, 332, 400 or 500 MHz considering different possibilites of input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * (vco1div2) clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * 400 200 100 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 400 250 125 0x03333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 400 332 166 0x0268D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * 400 400 200 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 500 200 100 0x05000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * 500 250 125 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * 500 332 166 0x03031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 500 400 200 0x02800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * 500 500 250 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * 600 200 100 0x06000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 600 250 125 0x04CCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * 600 332 166 0x039D5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 600 400 200 0x03000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 600 500 250 0x02666
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * 664 200 100 0x06a38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 664 250 125 0x054FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 664 332 166 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 664 400 200 0x0351E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 664 500 250 0x02A7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * 800 200 100 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * 800 250 125 0x06666
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * 800 332 166 0x04D18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * 800 400 200 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * 800 500 250 0x03333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * --------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * sys rate configuration table is in descending order of divisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct frac_rate_tbl sys_synth_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {.div = 0x08000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {.div = 0x06a38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {.div = 0x06666},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {.div = 0x06000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {.div = 0x054FD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {.div = 0x05000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {.div = 0x04D18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {.div = 0x04CCE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {.div = 0x04000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {.div = 0x039D5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {.div = 0x0351E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {.div = 0x03333},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {.div = 0x03031},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {.div = 0x03000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {.div = 0x02A7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {.div = 0x02800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {.div = 0x0268D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {.div = 0x02666},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {.div = 0x02000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct aux_rate_tbl aux_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {.xscale = 5, .yscale = 122, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {.xscale = 10, .yscale = 204, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {.xscale = 4, .yscale = 25, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {.xscale = 4, .yscale = 21, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {.xscale = 5, .yscale = 18, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {.xscale = 2, .yscale = 6, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {.xscale = 5, .yscale = 12, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {.xscale = 2, .yscale = 4, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {.xscale = 5, .yscale = 18, .eq = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {.xscale = 1, .yscale = 3, .eq = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {.xscale = 5, .yscale = 12, .eq = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {.xscale = 1, .yscale = 2, .eq = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* gmac rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct aux_rate_tbl gmac_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* For gmac phy input clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* clcd rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct frac_rate_tbl clcd_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* i2s prescaler1 masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct aux_clk_masks i2s_prs1_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .eq_sel_mask = AUX_EQ_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .eq1_mask = AUX_EQ1_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .eq2_mask = AUX_EQ2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* i2s sclk (bit clock) syynthesizers masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct aux_clk_masks i2s_sclk_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .eq_sel_mask = AUX_EQ_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .eq1_mask = AUX_EQ1_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .eq2_mask = AUX_EQ2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* i2s prs1 aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct aux_rate_tbl i2s_prs1_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* For parent clk = 49.152 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {.xscale = 1, .yscale = 3, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* For parent clk = 49.152 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* i2s sclk aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct aux_rate_tbl i2s_sclk_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* For sclk = ref_clk * x/2/y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {.xscale = 1, .yscale = 4, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {.xscale = 1, .yscale = 2, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* adc rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* possible adc range is 2.5 MHz to 20 MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct aux_rate_tbl adc_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* For ahb = 166.67 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* General synth rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct frac_rate_tbl gen_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* clock parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "uart0_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "uart1_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "osc_25m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "i2s_src_pad_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "pll3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) void __init spear1340_clk_init(void __iomem *misc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct clk *clk, *clk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_register_clkdev(clk, "osc_32k_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clk_register_clkdev(clk, "osc_24m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk_register_clkdev(clk, "osc_25m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clk_register_clkdev(clk, "gmii_pad_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 12288000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* clock derived from 32 KHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) clk_register_clkdev(clk, NULL, "e0580000.rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* clock derived from 24 or 25 MHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* vco-pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SPEAR1340_PLL_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clk_register_clkdev(clk, "vco1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clk_register_clkdev(clk, "vco1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk_register_clkdev(clk1, "pll1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SPEAR1340_PLL_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk_register_clkdev(clk, "vco2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) clk_register_clkdev(clk, "vco2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) clk_register_clkdev(clk1, "pll2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SPEAR1340_PLL_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clk_register_clkdev(clk, "vco3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk_register_clkdev(clk, "vco3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) clk_register_clkdev(clk1, "pll3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) clk_register_clkdev(clk, "vco4_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clk_register_clkdev(clk1, "pll4_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) clk_register_clkdev(clk, "pll5_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_register_clkdev(clk, "pll6_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* vco div n clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) clk_register_clkdev(clk, "vco1div2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk_register_clkdev(clk, "vco1div4_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) clk_register_clkdev(clk, "vco2div2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clk_register_clkdev(clk, "vco3div2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk_register_clkdev(clk, NULL, "e07008c4.thermal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* clock derived from pll4 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) clk_register_clkdev(clk, "ddr_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* clock derived from pll1 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ARRAY_SIZE(sys_synth_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clk_register_clkdev(clk, "sys_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ARRAY_SIZE(amba_synth_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clk_register_clkdev(clk, "amba_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clk_register_clkdev(clk, "sys_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) clk_register_clkdev(clk, "cpu_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clk_register_clkdev(clk, "cpu_div3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_register_clkdev(clk, NULL, "ec800620.wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_register_clkdev(clk, NULL, "smp_twd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_register_clkdev(clk, "ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk_register_clkdev(clk, "apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* gpt clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SPEAR1340_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_register_clkdev(clk, "gpt0_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) clk_register_clkdev(clk, NULL, "gpt0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SPEAR1340_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_register_clkdev(clk, "gpt1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_register_clkdev(clk, NULL, "gpt1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SPEAR1340_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_register_clkdev(clk, "gpt2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) clk_register_clkdev(clk, NULL, "gpt2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SPEAR1340_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clk_register_clkdev(clk, "gpt3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk_register_clkdev(clk, NULL, "gpt3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) clk_register_clkdev(clk, "uart0_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ARRAY_SIZE(uart0_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SPEAR1340_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) clk_register_clkdev(clk, "uart0_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SPEAR1340_UART0_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) clk_register_clkdev(clk, NULL, "e0000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) clk_register_clkdev(clk, "uart1_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SPEAR1340_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) clk_register_clkdev(clk, "uart1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) clk_register_clkdev(clk, NULL, "b4100000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) SPEAR1340_SDHCI_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) clk_register_clkdev(clk, NULL, "b3000000.sdhci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SPEAR1340_CFXD_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) clk_register_clkdev(clk, NULL, "b2800000.cf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) clk_register_clkdev(clk, NULL, "arasan_xd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) clk_register_clkdev(clk, "c3_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ARRAY_SIZE(c3_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SPEAR1340_C3_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) clk_register_clkdev(clk, "c3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) clk_register_clkdev(clk, NULL, "e1800000.c3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* gmac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ARRAY_SIZE(gmac_phy_input_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk_register_clkdev(clk, "phy_input_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) clk_register_clkdev(clk, "phy_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clk_register_clkdev(clk, "stmmacphy.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* clcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ARRAY_SIZE(clcd_synth_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) SPEAR1340_CLCD_SYNT_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ARRAY_SIZE(clcd_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk_register_clkdev(clk, "clcd_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ARRAY_SIZE(clcd_pixel_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clk_register_clkdev(clk, NULL, "e1000000.clcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) clk_register_clkdev(clk, "i2s_src_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) &i2s_prs1_masks, i2s_prs1_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ARRAY_SIZE(i2s_ref_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* clock derived from ahb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) clk_register_clkdev(clk, NULL, "e0280000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) clk_register_clkdev(clk, NULL, "b4000000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) clk_register_clkdev(clk, NULL, "ea800000.dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) clk_register_clkdev(clk, NULL, "eb000000.dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) clk_register_clkdev(clk, NULL, "e2000000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) clk_register_clkdev(clk, NULL, "b0000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) clk_register_clkdev(clk, NULL, "ea000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) clk_register_clkdev(clk, NULL, "e4000000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clk_register_clkdev(clk, NULL, "e4800000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) clk_register_clkdev(clk, NULL, "e5000000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clk_register_clkdev(clk, NULL, "e5800000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clk_register_clkdev(clk, NULL, "e3800000.otg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) clk_register_clkdev(clk, NULL, "b1000000.pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk_register_clkdev(clk, NULL, "b1000000.ahci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) clk_register_clkdev(clk, "sysram0_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) clk_register_clkdev(clk, "sysram1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) clk_register_clkdev(clk, "adc_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SPEAR1340_ADC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) clk_register_clkdev(clk, NULL, "e0080000.adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* clock derived from apb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clk_register_clkdev(clk, NULL, "e0100000.spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) clk_register_clkdev(clk, NULL, "e0600000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) clk_register_clkdev(clk, NULL, "e0680000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) clk_register_clkdev(clk, NULL, "e0300000.kbd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* RAS clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ARRAY_SIZE(gen_synth0_1_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ARRAY_SIZE(gen_synth2_3_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) clk_register_clkdev(clk, "gen_syn0_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) clk_register_clkdev(clk, "gen_syn1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) clk_register_clkdev(clk, "gen_syn2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) clk_register_clkdev(clk, "gen_syn3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SPEAR1340_MALI_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) clk_register_clkdev(clk, NULL, "mali");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clk_register_clkdev(clk, NULL, "spear_cec.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) clk_register_clkdev(clk, NULL, "spear_cec.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ARRAY_SIZE(spdif_out_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) clk_register_clkdev(clk, "spdif_out_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ARRAY_SIZE(spdif_in_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) clk_register_clkdev(clk, "spdif_in_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) clk_register_clkdev(clk, NULL, "acp_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) clk_register_clkdev(clk, NULL, "e2800000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) clk_register_clkdev(clk, NULL, "video_dec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) clk_register_clkdev(clk, NULL, "video_enc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) clk_register_clkdev(clk, NULL, "spear_vip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) clk_register_clkdev(clk, NULL, "d0200000.cam0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) clk_register_clkdev(clk, NULL, "d0300000.cam1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) clk_register_clkdev(clk, NULL, "d0400000.cam2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) clk_register_clkdev(clk, NULL, "d0500000.cam3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) clk_register_clkdev(clk, NULL, "e0180000.pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags