^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-spear13xx/spear1310_clock.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPEAr1310 machine clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PLL related registers and bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPEAR1310_PLL_CFG (misc_base + 0x210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PLL_CFG bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPEAR1310_RAS_SYNT_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPEAR1310_PLL_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPEAR1310_PLL3_CLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPEAR1310_PLL2_CLK_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPEAR1310_PLL1_CLK_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPEAR1310_PLL1_CTR (misc_base + 0x214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPEAR1310_PLL1_FRQ (misc_base + 0x218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPEAR1310_PLL2_CTR (misc_base + 0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPEAR1310_PLL2_FRQ (misc_base + 0x224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPEAR1310_PLL3_CTR (misc_base + 0x22C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPEAR1310_PLL3_FRQ (misc_base + 0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPEAR1310_PLL4_CTR (misc_base + 0x238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PERIP_CLK_CFG bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPEAR1310_GPT_OSC24_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPEAR1310_GPT_APB_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPEAR1310_GPT_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPEAR1310_GPT3_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPEAR1310_GPT2_CLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPEAR1310_GPT1_CLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPEAR1310_GPT0_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPEAR1310_UART_CLK_PLL5_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPEAR1310_UART_CLK_OSC24_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPEAR1310_UART_CLK_SYNT_VAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPEAR1310_UART_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPEAR1310_UART_CLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPEAR1310_AUX_CLK_PLL5_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPEAR1310_AUX_CLK_SYNT_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPEAR1310_CLCD_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPEAR1310_CLCD_CLK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPEAR1310_C3_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPEAR1310_C3_CLK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPEAR1310_GMAC_PHY_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* I2S_CLK_CFG register mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPEAR1310_I2S_SCLK_X_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPEAR1310_I2S_SCLK_Y_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPEAR1310_I2S_REF_SEL_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPEAR1310_I2S_REF_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPEAR1310_I2S_SRC_CLK_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Check Fractional synthesizer reg masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* PERIP1_CLK_ENB register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPEAR1310_RTC_CLK_ENB 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPEAR1310_ADC_CLK_ENB 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPEAR1310_C3_CLK_ENB 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPEAR1310_JPEG_CLK_ENB 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPEAR1310_CLCD_CLK_ENB 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPEAR1310_DMA_CLK_ENB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SPEAR1310_GPIO1_CLK_ENB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SPEAR1310_GPIO0_CLK_ENB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SPEAR1310_GPT1_CLK_ENB 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SPEAR1310_GPT0_CLK_ENB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPEAR1310_I2S0_CLK_ENB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPEAR1310_I2S1_CLK_ENB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPEAR1310_I2C0_CLK_ENB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SPEAR1310_SSP_CLK_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SPEAR1310_UART_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SPEAR1310_UOC_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPEAR1310_UHC1_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPEAR1310_UHC0_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SPEAR1310_GMAC_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SPEAR1310_CFXD_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SPEAR1310_SDHCI_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SPEAR1310_SMI_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SPEAR1310_FSMC_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SPEAR1310_SYSRAM0_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SPEAR1310_SYSRAM1_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SPEAR1310_SYSROM_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SPEAR1310_BUS_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* PERIP2_CLK_ENB register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SPEAR1310_THSENS_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SPEAR1310_ACP_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SPEAR1310_GPT3_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SPEAR1310_GPT2_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SPEAR1310_KBD_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPEAR1310_CPU_DBG_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SPEAR1310_DDR_CORE_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SPEAR1310_DDR_CTRL_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* RAS_CLK_ENB register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SPEAR1310_SYNT3_CLK_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SPEAR1310_SYNT2_CLK_ENB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SPEAR1310_SYNT1_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SPEAR1310_SYNT0_CLK_ENB 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SPEAR1310_PCLK3_CLK_ENB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SPEAR1310_PCLK2_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SPEAR1310_PCLK1_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SPEAR1310_PCLK0_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SPEAR1310_PLL3_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SPEAR1310_PLL2_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SPEAR1310_C125M_PAD_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SPEAR1310_C30M_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SPEAR1310_C48M_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SPEAR1310_OSC_25M_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SPEAR1310_OSC_32K_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SPEAR1310_OSC_24M_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SPEAR1310_PCLK_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SPEAR1310_ACLK_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* RAS Area Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SPEAR1310_SSP1_CLK_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SPEAR1310_SSP1_CLK_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SPEAR1310_TDM_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SPEAR1310_TDM2_CLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SPEAR1310_TDM1_CLK_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SPEAR1310_I2C_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SPEAR1310_I2C7_CLK_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SPEAR1310_I2C6_CLK_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SPEAR1310_I2C5_CLK_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SPEAR1310_I2C4_CLK_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SPEAR1310_I2C3_CLK_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SPEAR1310_I2C2_CLK_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SPEAR1310_I2C1_CLK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SPEAR1310_GPT64_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SPEAR1310_GPT64_CLK_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SPEAR1310_RAS_UART_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SPEAR1310_UART5_CLK_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SPEAR1310_UART4_CLK_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SPEAR1310_UART3_CLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SPEAR1310_UART2_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SPEAR1310_UART1_CLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SPEAR1310_PCI_CLK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SPEAR1310_PCI_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SPEAR1310_PHY_CLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SPEAR1310_CAN1_CLK_ENB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SPEAR1310_CAN0_CLK_ENB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SPEAR1310_GPT64_CLK_ENB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SPEAR1310_SSP1_CLK_ENB 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SPEAR1310_I2C7_CLK_ENB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SPEAR1310_I2C6_CLK_ENB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SPEAR1310_I2C5_CLK_ENB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SPEAR1310_I2C4_CLK_ENB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SPEAR1310_I2C3_CLK_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SPEAR1310_I2C2_CLK_ENB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SPEAR1310_I2C1_CLK_ENB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SPEAR1310_UART5_CLK_ENB 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SPEAR1310_UART4_CLK_ENB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SPEAR1310_UART3_CLK_ENB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SPEAR1310_UART2_CLK_ENB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SPEAR1310_UART1_CLK_ENB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SPEAR1310_RS485_1_CLK_ENB 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SPEAR1310_RS485_0_CLK_ENB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SPEAR1310_TDM2_CLK_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SPEAR1310_TDM1_CLK_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SPEAR1310_PCI_CLK_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SPEAR1310_GMII_CLK_ENB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SPEAR1310_MII2_CLK_ENB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SPEAR1310_MII1_CLK_ENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SPEAR1310_MII0_CLK_ENB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SPEAR1310_ESRAM_CLK_ENB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static DEFINE_SPINLOCK(_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* pll rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct pll_rate_tbl pll_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* PCLK 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* vco-pll4 rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct pll_rate_tbl pll4_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct aux_rate_tbl aux_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* For VCO1div2 = 500 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* gmac rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct aux_rate_tbl gmac_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* For gmac phy input clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* clcd rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct frac_rate_tbl clcd_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* i2s prescaler1 masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct aux_clk_masks i2s_prs1_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .eq_sel_mask = AUX_EQ_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .eq1_mask = AUX_EQ1_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .eq2_mask = AUX_EQ2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* i2s sclk (bit clock) syynthesizers masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct aux_clk_masks i2s_sclk_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .eq_sel_mask = AUX_EQ_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .eq1_mask = AUX_EQ1_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .eq2_mask = AUX_EQ2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* i2s prs1 aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct aux_rate_tbl i2s_prs1_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* For parent clk = 49.152 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {.xscale = 1, .yscale = 3, .eq = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* For parent clk = 49.152 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* i2s sclk aux rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct aux_rate_tbl i2s_sclk_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* For i2s_ref_clk = 12.288MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* adc rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* possible adc range is 2.5 MHz to 20 MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct aux_rate_tbl adc_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* For ahb = 166.67 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* General synth rate configuration table, in ascending order of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct frac_rate_tbl gen_rtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* For vco1div4 = 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {.div = 0x14000}, /* 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {.div = 0x0A000}, /* 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {.div = 0x05000}, /* 100 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {.div = 0x02000}, /* 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* clock parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "osc_25m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "i2s_src_pad_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "pll3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "pll2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "ras_pll2_clk", "ras_syn0_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "ras_pll2_clk", "ras_syn0_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "ras_plclk0_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct clk *clk, *clk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clk_register_clkdev(clk, "osc_32k_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) clk_register_clkdev(clk, "osc_24m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk_register_clkdev(clk, "osc_25m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clk_register_clkdev(clk, "gmii_pad_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 12288000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* clock derived from 32 KHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) clk_register_clkdev(clk, NULL, "e0580000.rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* clock derived from 24 or 25 MHz osc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* vco-pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SPEAR1310_PLL_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk_register_clkdev(clk, "vco1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk_register_clkdev(clk, "vco1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) clk_register_clkdev(clk1, "pll1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SPEAR1310_PLL_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_register_clkdev(clk, "vco2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) clk_register_clkdev(clk, "vco2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) clk_register_clkdev(clk1, "pll2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SPEAR1310_PLL_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_register_clkdev(clk, "vco3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) clk_register_clkdev(clk, "vco3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) clk_register_clkdev(clk1, "pll3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk_register_clkdev(clk, "vco4_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clk_register_clkdev(clk1, "pll4_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clk_register_clkdev(clk, "pll5_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk_register_clkdev(clk, "pll6_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* vco div n clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk_register_clkdev(clk, "vco1div2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) clk_register_clkdev(clk, "vco1div4_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clk_register_clkdev(clk, "vco2div2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) clk_register_clkdev(clk, "vco3div2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk_register_clkdev(clk, NULL, "spear_thermal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* clock derived from pll4 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_register_clkdev(clk, "ddr_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* clock derived from pll1 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) clk_register_clkdev(clk, "cpu_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_register_clkdev(clk, NULL, "ec800620.wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) clk_register_clkdev(clk, NULL, "smp_twd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) clk_register_clkdev(clk, "ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) clk_register_clkdev(clk, "apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* gpt clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SPEAR1310_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clk_register_clkdev(clk, "gpt0_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) clk_register_clkdev(clk, NULL, "gpt0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SPEAR1310_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) clk_register_clkdev(clk, "gpt1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk_register_clkdev(clk, NULL, "gpt1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SPEAR1310_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clk_register_clkdev(clk, "gpt2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk_register_clkdev(clk, NULL, "gpt2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SPEAR1310_GPT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) clk_register_clkdev(clk, "gpt3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) clk_register_clkdev(clk, NULL, "gpt3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clk_register_clkdev(clk, "uart_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ARRAY_SIZE(uart0_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SPEAR1310_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) clk_register_clkdev(clk, "uart0_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SPEAR1310_UART_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clk_register_clkdev(clk, NULL, "e0000000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_register_clkdev(clk, NULL, "b3000000.sdhci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) clk_register_clkdev(clk, NULL, "b2800000.cf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) clk_register_clkdev(clk, NULL, "arasan_xd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) clk_register_clkdev(clk, "c3_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ARRAY_SIZE(c3_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SPEAR1310_C3_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_register_clkdev(clk, "c3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) clk_register_clkdev(clk, NULL, "c3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* gmac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ARRAY_SIZE(gmac_phy_input_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) clk_register_clkdev(clk, "phy_input_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) clk_register_clkdev(clk, "phy_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_register_clkdev(clk, "stmmacphy.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* clcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ARRAY_SIZE(clcd_synth_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SPEAR1310_CLCD_SYNT_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ARRAY_SIZE(clcd_rtbl), &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) clk_register_clkdev(clk, "clcd_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ARRAY_SIZE(clcd_pixel_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) clk_register_clkdev(clk, NULL, "e1000000.clcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) clk_register_clkdev(clk, "i2s_src_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ARRAY_SIZE(i2s_ref_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &i2s_sclk_masks, i2s_sclk_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* clock derived from ahb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) clk_register_clkdev(clk, NULL, "e0280000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) clk_register_clkdev(clk, NULL, "ea800000.dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clk_register_clkdev(clk, NULL, "eb000000.dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) clk_register_clkdev(clk, NULL, "b2000000.jpeg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) clk_register_clkdev(clk, NULL, "e2000000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) clk_register_clkdev(clk, NULL, "b0000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clk_register_clkdev(clk, NULL, "ea000000.flash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) clk_register_clkdev(clk, NULL, "e4000000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) clk_register_clkdev(clk, NULL, "e4800000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) clk_register_clkdev(clk, NULL, "e5000000.ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) clk_register_clkdev(clk, NULL, "e5800000.ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) clk_register_clkdev(clk, NULL, "e3800000.otg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) clk_register_clkdev(clk, NULL, "b1000000.pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_register_clkdev(clk, NULL, "b1000000.ahci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) clk_register_clkdev(clk, NULL, "b1800000.pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) clk_register_clkdev(clk, NULL, "b1800000.ahci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) clk_register_clkdev(clk, NULL, "b4000000.pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) clk_register_clkdev(clk, NULL, "b4000000.ahci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) clk_register_clkdev(clk, "sysram0_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) clk_register_clkdev(clk, "sysram1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) clk_register_clkdev(clk, "adc_syn_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SPEAR1310_ADC_CLK_ENB, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) clk_register_clkdev(clk, NULL, "e0080000.adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* clock derived from apb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) clk_register_clkdev(clk, NULL, "e0100000.spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) clk_register_clkdev(clk, NULL, "e0600000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) clk_register_clkdev(clk, NULL, "e0680000.gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) clk_register_clkdev(clk, NULL, "e0180000.i2s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) clk_register_clkdev(clk, NULL, "e0200000.i2s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) clk_register_clkdev(clk, NULL, "e0300000.kbd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* RAS clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ARRAY_SIZE(gen_synth0_1_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ARRAY_SIZE(gen_synth2_3_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) clk_register_clkdev(clk, "gen_syn0_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) clk_register_clkdev(clk, "gen_syn1_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) clk_register_clkdev(clk, "gen_syn2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clk_register_clkdev(clk, "gen_syn3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) clk_register_clkdev(clk, "ras_pll2_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clk_register_clkdev(clk, "ras_pll3_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) clk_register_clkdev(clk, "ras_tx125_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 30000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) clk_register_clkdev(clk, "ras_30m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) clk_register_clkdev(clk, "ras_48m_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) clk_register_clkdev(clk, "ras_ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) clk_register_clkdev(clk, "ras_apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) clk_register_clkdev(clk, NULL, "c_can_platform.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) clk_register_clkdev(clk, NULL, "c_can_platform.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) clk_register_clkdev(clk, NULL, "5c400000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) clk_register_clkdev(clk, NULL, "5c500000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) clk_register_clkdev(clk, NULL, "5c600000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) clk_register_clkdev(clk, NULL, "5c700000.eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) smii_rgmii_phy_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ARRAY_SIZE(smii_rgmii_phy_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) SPEAR1310_PHY_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) clk_register_clkdev(clk, "stmmacphy.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) clk_register_clkdev(clk, "stmmacphy.2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) clk_register_clkdev(clk, "stmmacphy.4", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SPEAR1310_PHY_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) clk_register_clkdev(clk, "stmmacphy.3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) clk_register_clkdev(clk, "uart1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) clk_register_clkdev(clk, NULL, "5c800000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) clk_register_clkdev(clk, "uart2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) clk_register_clkdev(clk, NULL, "5c900000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) clk_register_clkdev(clk, "uart3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) clk_register_clkdev(clk, NULL, "5ca00000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) clk_register_clkdev(clk, "uart4_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) clk_register_clkdev(clk, NULL, "5cb00000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) clk_register_clkdev(clk, "uart5_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) clk_register_clkdev(clk, NULL, "5cc00000.serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) clk_register_clkdev(clk, "i2c1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) clk_register_clkdev(clk, NULL, "5cd00000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) clk_register_clkdev(clk, "i2c2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) clk_register_clkdev(clk, NULL, "5ce00000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) clk_register_clkdev(clk, "i2c3_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) clk_register_clkdev(clk, NULL, "5cf00000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) clk_register_clkdev(clk, "i2c4_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) clk_register_clkdev(clk, NULL, "5d000000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) clk_register_clkdev(clk, "i2c5_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clk_register_clkdev(clk, NULL, "5d100000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) clk_register_clkdev(clk, "i2c6_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clk_register_clkdev(clk, NULL, "5d200000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SPEAR1310_I2C_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) clk_register_clkdev(clk, "i2c7_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) clk_register_clkdev(clk, NULL, "5d300000.i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) clk_register_clkdev(clk, "ssp1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) clk_register_clkdev(clk, NULL, "5d400000.spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) SPEAR1310_PCI_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) clk_register_clkdev(clk, "pci_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk_register_clkdev(clk, NULL, "pci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SPEAR1310_TDM_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) clk_register_clkdev(clk, "tdm1_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SPEAR1310_TDM_CLK_MASK, 0, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) clk_register_clkdev(clk, "tdm2_mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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