^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * VCO-PLL clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "clk-vco-pll: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * DOC: VCO-PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * VCO and PLL rate are derived from following equations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * In normal mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * vco = (2 * M[15:8] * Fin)/N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * In Dithered mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * vco = (2 * M[15:0] * Fin)/(256 * N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * pll_rate = pll/2^p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * vco and pll are very closely bound to each other, "vco needs to program:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * mode, m & n" and "pll needs to program p", both share common enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * clk_register_vco_pll() registers instances of both vco & pll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * set_rate to vco. A single rate table exists for both the clocks, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * configures m, n and p.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* PLL_CTR register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLL_MODE_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLL_MODE_FRACTION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLL_MODE_DITH_DSM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLL_MODE_DITH_SSM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PLL_MODE_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLL_MODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLL_ENABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLL_LOCK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLL_LOCK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PLL FRQ register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLL_NORM_FDBK_M_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLL_NORM_FDBK_M_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLL_DITH_FDBK_M_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLL_DITH_FDBK_M_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLL_DIV_P_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLL_DIV_P_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLL_DIV_N_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLL_DIV_N_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Calculates pll clk rate for specific value of mode, m, n and p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long prate, int index, unsigned long *pll_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long rate = prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mode = rtbl[index].mode ? 256 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (pll_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return rate * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long *prate, int *index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long prev_rate, vco_prev_rate, rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long vco_parent_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clk_hw_get_rate(clk_hw_get_parent(clk_hw_get_parent(hw)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!prate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pr_err("%s: prate is must for pll clk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) prev_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) vco_prev_rate = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (drate < rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* previous clock was best */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (*index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rate = prev_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *prate = vco_prev_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (*index)--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return clk_pll_round_rate_index(hw, drate, prate, &unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (pll->vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_lock_irqsave(pll->vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) p = readl_relaxed(pll->vco->cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (pll->vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_unlock_irqrestore(pll->vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return parent_rate / (1 << p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct pll_rate_tbl *rtbl = pll->vco->rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long flags = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_pll_round_rate_index(hw, drate, NULL, &i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (pll->vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spin_lock_irqsave(pll->vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val = readl_relaxed(pll->vco->cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel_relaxed(val, pll->vco->cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (pll->vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(pll->vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct clk_ops clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .round_rate = clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline unsigned long vco_calc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long prate, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct clk_vco *vco = to_clk_vco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return pll_calc_rate(vco->rtbl, prate, index, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clk_vco *vco = to_clk_vco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return clk_round_rate_index(hw, drate, *prate, vco_calc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) vco->rtbl_cnt, &unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct clk_vco *vco = to_clk_vco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int num = 2, den = 0, val, mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_lock_irqsave(vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val = readl_relaxed(vco->cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spin_unlock_irqrestore(vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* calculate numerator & denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Dithered mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) den *= 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!den) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) WARN(1, "%s: denominator can't be zero\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return (((parent_rate / 10000) * num) / den) * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Configures new clock rate of vco */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct clk_vco *vco = to_clk_vco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct pll_rate_tbl *rtbl = vco->rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long flags = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) &i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_lock_irqsave(vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) val = readl_relaxed(vco->mode_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel_relaxed(val, vco->mode_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) val = readl_relaxed(vco->cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (rtbl[i].mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PLL_DITH_FDBK_M_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PLL_NORM_FDBK_M_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel_relaxed(val, vco->cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (vco->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(vco->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct clk_ops clk_vco_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .recalc_rate = clk_vco_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .round_rate = clk_vco_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .set_rate = clk_vco_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const char *vco_gate_name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long flags, void __iomem *mode_reg, void __iomem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spinlock_t *lock, struct clk **pll_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct clk **vco_gate_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct clk_vco *vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct clk_init_data vco_init, pll_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const char **vco_parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) !rtbl || !rtbl_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_err("Invalid arguments passed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) vco = kzalloc(sizeof(*vco), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto free_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* struct clk_vco assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) vco->mode_reg = mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) vco->cfg_reg = cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) vco->rtbl = rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) vco->rtbl_cnt = rtbl_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) vco->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) vco->hw.init = &vco_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pll->vco = vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pll->hw.init = &pll_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (vco_gate_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (IS_ERR_OR_NULL(tvco_gate_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (vco_gate_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *vco_gate_clk = tvco_gate_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) vco_parent_name = &vco_gate_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) vco_parent_name = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) vco_init.name = vco_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) vco_init.ops = &clk_vco_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) vco_init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) vco_init.parent_names = vco_parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) vco_init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pll_init.name = pll_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pll_init.ops = &clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pll_init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pll_init.parent_names = &vco_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pll_init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) vco_clk = clk_register(NULL, &vco->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (IS_ERR_OR_NULL(vco_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) tpll_clk = clk_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (IS_ERR_OR_NULL(tpll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *pll_clk = tpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return vco_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) free_pll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) free_vco:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) kfree(vco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) pr_err("Failed to register vco pll clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags