^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Fractional Synthesizer clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "clk-frac-synth: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DIV_FACTOR_MASK 0x1FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * DOC: Fractional Synthesizer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Fout from synthesizer can be given from below equation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Fout= Fin/2*div (division factor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * div is 17 bits:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0-13 (fractional part)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 14-16 (integer part)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * div is (16-14 bits).(13-0 bits) (in binary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Fout = Fin/(2 * div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Fout = ((Fin / 10000)/(2 * div)) * 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * div << 14 simply 17 bit value written at register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Max error due to scaling down by 10000 is 10 KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk_frac *frac = to_clk_frac(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct frac_rate_tbl *rtbl = frac->rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) prate /= 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) prate <<= 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) prate /= (2 * rtbl[index].div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) prate *= 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_frac *frac = to_clk_frac(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return clk_round_rate_index(hw, drate, *prate, frac_calc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) frac->rtbl_cnt, &unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk_frac *frac = to_clk_frac(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int div = 1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (frac->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spin_lock_irqsave(frac->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = readl_relaxed(frac->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (frac->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_unlock_irqrestore(frac->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) div = val & DIV_FACTOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) parent_rate = parent_rate / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) parent_rate = (parent_rate << 14) / (2 * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return parent_rate * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Configures new clock rate of frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_frac *frac = to_clk_frac(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct frac_rate_tbl *rtbl = frac->rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long flags = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (frac->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock_irqsave(frac->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= rtbl[i].div & DIV_FACTOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel_relaxed(val, frac->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (frac->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spin_unlock_irqrestore(frac->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct clk_ops clk_frac_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .recalc_rate = clk_frac_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .round_rate = clk_frac_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .set_rate = clk_frac_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct clk *clk_register_frac(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long flags, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk_frac *frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_err("Invalid arguments passed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) frac = kzalloc(sizeof(*frac), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!frac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* struct clk_frac assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) frac->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) frac->rtbl = rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) frac->rtbl_cnt = rtbl_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) frac->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) frac->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) init.ops = &clk_frac_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk = clk_register(NULL, &frac->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!IS_ERR_OR_NULL(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pr_err("clk register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) kfree(frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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