^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Auxiliary Synthesizer clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "clk-aux-synth: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * DOC: Auxiliary Synthesizer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Aux synth gives rate for different values of eq, x and y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Fout from synthesizer can be given from two equations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Fout1 = (Fin * X/Y)/2 EQ1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Fout2 = Fin * X/Y EQ2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct aux_clk_masks default_aux_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .eq_sel_mask = AUX_EQ_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .eq_sel_shift = AUX_EQ_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .eq1_mask = AUX_EQ1_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .eq2_mask = AUX_EQ2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .xscale_sel_mask = AUX_XSCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .xscale_sel_shift = AUX_XSCALE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .yscale_sel_mask = AUX_YSCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .yscale_sel_shift = AUX_YSCALE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .enable_bit = AUX_SYNT_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk_aux *aux = to_clk_aux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct aux_rate_tbl *rtbl = aux->rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 eq = rtbl[index].eq ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return (((prate / 10000) * rtbl[index].xscale) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (rtbl[index].yscale * eq)) * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct clk_aux *aux = to_clk_aux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) aux->rtbl_cnt, &unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk_aux *aux = to_clk_aux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int num = 1, den = 1, val, eqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (aux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_lock_irqsave(aux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = readl_relaxed(aux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (aux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spin_unlock_irqrestore(aux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (eqn == aux->masks->eq1_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) den = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* calculate numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) num = (val >> aux->masks->xscale_sel_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) aux->masks->xscale_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* calculate denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) den *= (val >> aux->masks->yscale_sel_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) aux->masks->yscale_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (((parent_rate / 10000) * num) / den) * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Configures new clock rate of aux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_aux *aux = to_clk_aux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct aux_rate_tbl *rtbl = aux->rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long val, flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (aux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) spin_lock_irqsave(aux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = readl_relaxed(aux->reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) aux->masks->eq_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) aux->masks->xscale_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) aux->masks->yscale_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel_relaxed(val, aux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (aux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_unlock_irqrestore(aux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct clk_ops clk_aux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .recalc_rate = clk_aux_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .round_rate = clk_aux_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .set_rate = clk_aux_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const char *parent_name, unsigned long flags, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_aux *aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_err("Invalid arguments passed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) aux = kzalloc(sizeof(*aux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* struct clk_aux assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!masks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) aux->masks = &default_aux_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) aux->masks = masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) aux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) aux->rtbl = rtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) aux->rtbl_cnt = rtbl_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) aux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) aux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) init.name = aux_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) init.ops = &clk_aux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk = clk_register(NULL, &aux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_ERR_OR_NULL(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto free_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (gate_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct clk *tgate_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tgate_clk = clk_register_gate(NULL, gate_name, aux_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) aux->masks->enable_bit, 0, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR_OR_NULL(tgate_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto free_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (gate_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *gate_clk = tgate_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) free_aux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) kfree(aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pr_err("clk register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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