Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier:    GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef	__STRATIX10_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define	__STRATIX10_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) struct stratix10_clock_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	struct clk_onecell_data	clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct stratix10_pll_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	unsigned int		id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	const char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	const struct clk_parent_data	*parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u8			num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	unsigned long		flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	unsigned long		offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct stratix10_perip_c_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	unsigned int		id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	const char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	const char		*parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	const struct clk_parent_data	*parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u8			num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned long		flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned long		offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct stratix10_perip_cnt_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	unsigned int		id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	const char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	const char		*parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	const struct clk_parent_data	*parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u8			num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned long		flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned long		offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u8			fixed_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	unsigned long		bypass_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	unsigned long		bypass_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct stratix10_gate_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	unsigned int		id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	const char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	const char		*parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	const struct clk_parent_data	*parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	u8			num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	unsigned long		flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	unsigned long		gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	u8			gate_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	unsigned long		div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	u8			div_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	u8			div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	unsigned long		bypass_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u8			bypass_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	u8			fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk *s10_register_pll(const struct stratix10_pll_clock *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			     void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 				void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 				void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 				    void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *s10_register_gate(const struct stratix10_gate_clock *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			      void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif	/* __STRATIX10_CLK_H */