Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * based on drivers/clk/tegra/clk.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __SOCFPGA_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __SOCFPGA_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Clock Manager offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKMGR_CTRL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKMGR_BYPASS		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLKMGR_DBCTRL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKMGR_L4SRC		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLKMGR_PERPLL_SRC	0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOCFPGA_MAX_PARENTS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define streq(a, b) (strcmp((a), (b)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern void __iomem *clk_mgr_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern void __iomem *clk_mgr_a10_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __init socfpga_pll_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __init socfpga_periph_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __init socfpga_gate_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void socfpga_a10_pll_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void socfpga_a10_periph_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void socfpga_a10_gate_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct socfpga_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct clk_gate	hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct socfpga_gate_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct clk_gate hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u32 fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	void __iomem *div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	void __iomem *bypass_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct regmap *sys_mgr_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u32 width;	/* only valid if div_reg != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	u32 shift;	/* only valid if div_reg != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	u32 clk_phase[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct socfpga_periph_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct clk_gate hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u32 fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	void __iomem *div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	void __iomem *bypass_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	u32 width;      /* only valid if div_reg != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	u32 shift;      /* only valid if div_reg != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* SOCFPGA_CLK_H */