Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Copyright 2011-2012 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Based from clk-highbank.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CLK_OF_DECLARE(socfpga_a10_pll_clk, "altr,socfpga-a10-pll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	       socfpga_a10_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) CLK_OF_DECLARE(socfpga_a10_perip_clk, "altr,socfpga-a10-perip-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	       socfpga_a10_periph_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) CLK_OF_DECLARE(socfpga_a10_gate_clk, "altr,socfpga-a10-gate-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	       socfpga_a10_gate_init);