^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011-2012 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based from clk-highbank.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Clock bypass bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAINPLL_BYPASS (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SDRAMPLL_BYPASS (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SDRAMPLL_SRC_BYPASS (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PERPLL_BYPASS (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PERPLL_SRC_BYPASS (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOCFPGA_PLL_BG_PWRDWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SOCFPGA_PLL_EXT_ENA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOCFPGA_PLL_PWR_DOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SOCFPGA_PLL_DIVF_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SOCFPGA_PLL_DIVQ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_MGR_PLL_CLK_SRC_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_MGR_PLL_CLK_SRC_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *clk_mgr_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long divf, divq, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long long vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (bypass & MAINPLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) vco_freq = (unsigned long long)parent_rate * (divf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) do_div(vco_freq, (1 + divq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return (unsigned long)vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static u8 clk_pll_get_parent(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 pll_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pll_src = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_MGR_PLL_CLK_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct clk_ops clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .get_parent = clk_pll_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static __init struct clk *__socfpga_pll_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const struct clk_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct socfpga_pll *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char *parent_name[SOCFPGA_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device_node *clkmgr_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) of_property_read_u32(node, "reg", ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (WARN_ON(!pll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) of_node_put(clkmgr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BUG_ON(!clk_mgr_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pll_clk->hw.reg = clk_mgr_base_addr + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) init.parent_names = parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pll_clk->hw.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk = clk_register(NULL, &pll_clk->hw.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) kfree(pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __init socfpga_pll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __socfpga_pll_init(node, &clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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