^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "stratix10-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Clock Manager offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_MGR_PLL_CLK_SRC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_MGR_PLL_CLK_SRC_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PLL Clock enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SOCFPGA_PLL_POWER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SOCFPGA_PLL_RESET_MASK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOCFPGA_PLL_REFDIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SOCFPGA_PLL_AREFDIV_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SOCFPGA_PLL_DREFDIV_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOCFPGA_PLL_DREFDIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SOCFPGA_PLL_MDIV_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOCFPGA_PLL_MDIV_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOCFPGA_AGILEX_PLL_MDIV_MASK 0x000003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SWCTRLBTCLKSEL_MASK 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SWCTRLBTCLKSEL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SOCFPGA_BOOT_CLK "boot_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long arefdiv, reg, mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long long vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* read VCO1 reg for numerator and denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) reg = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) vco_freq = (unsigned long long)parent_rate / arefdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Read mdiv and fdiv from the fdbck register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) reg = readl(socfpgaclk->hw.reg + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) vco_freq = (unsigned long long)vco_freq * mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return (unsigned long)vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long long vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* read VCO1 reg for numerator and denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) reg = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) vco_freq = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) do_div(vco_freq, refdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Read mdiv and fdiv from the fdbck register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = readl(socfpgaclk->hw.reg + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return (unsigned long)vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) div = ((readl(socfpgaclk->hw.reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SWCTRLBTCLKSEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SWCTRLBTCLKSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) div += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return parent_rate /= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static u8 clk_pll_get_parent(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 pll_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pll_src = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_MGR_PLL_CLK_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static u8 clk_boot_get_parent(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 pll_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pll_src = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SWCTRLBTCLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int clk_pll_prepare(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Bring PLL out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) reg = readl(socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg |= SOCFPGA_PLL_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(reg, socfpgaclk->hw.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct clk_ops agilex_clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .recalc_rate = agilex_clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .get_parent = clk_pll_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .prepare = clk_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct clk_ops clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .get_parent = clk_pll_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .prepare = clk_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct clk_ops clk_boot_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .recalc_rate = clk_boot_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .get_parent = clk_boot_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .prepare = clk_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct socfpga_pll *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char *name = clks->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (WARN_ON(!pll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pll_clk->hw.reg = reg + clks->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (streq(name, SOCFPGA_BOOT_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) init.ops = &clk_boot_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) init.ops = &clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) init.flags = clks->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) init.num_parents = clks->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) init.parent_data = clks->parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pll_clk->hw.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk = clk_register(NULL, &pll_clk->hw.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) kfree(pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct socfpga_pll *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const char *name = clks->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (WARN_ON(!pll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pll_clk->hw.reg = reg + clks->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (streq(name, SOCFPGA_BOOT_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) init.ops = &clk_boot_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) init.ops = &agilex_clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) init.flags = clks->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) init.num_parents = clks->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) init.parent_data = clks->parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pll_clk->hw.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk = clk_register(NULL, &pll_clk->hw.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) kfree(pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags