Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright 2011-2012 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based from clk-highbank.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SOCFPGA_NAND_CLK		"nand_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SOCFPGA_NAND_X_CLK		"nand_x_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SOCFPGA_MMC_CLK			"sdmmc_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SOCFPGA_GPIO_DB_CLK_OFFSET	0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* SDMMC Group for System Manager defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 l4_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 perpll_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	const char *name = clk_hw_get_name(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (streq(name, SOCFPGA_L4_MP_CLK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		return l4_src &= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (streq(name, SOCFPGA_L4_SP_CLK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return !!(l4_src & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (streq(name, SOCFPGA_MMC_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return perpll_src &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (streq(name, SOCFPGA_NAND_CLK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	    streq(name, SOCFPGA_NAND_X_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return (perpll_src >> 2) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* QSPI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return (perpll_src >> 4) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 src_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	const char *name = clk_hw_get_name(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (streq(name, SOCFPGA_L4_MP_CLK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		src_reg &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		src_reg |= parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		src_reg &= ~0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		src_reg |= (parent << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		if (streq(name, SOCFPGA_MMC_CLK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			src_reg &= ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			src_reg |= parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		} else if (streq(name, SOCFPGA_NAND_CLK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			streq(name, SOCFPGA_NAND_X_CLK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			src_reg &= ~0xC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			src_reg |= (parent << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		} else {/* QSPI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			src_reg &= ~0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			src_reg |= (parent << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 div = 1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (socfpgaclk->fixed_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		div = socfpgaclk->fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	else if (socfpgaclk->div_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		val &= GENMASK(socfpgaclk->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		/* Check for GPIO_DB_CLK by its offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			div = val + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			div = (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int socfpga_clk_prepare(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct regmap *sys_mgr_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 hs_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 clk_phase[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		if (IS_ERR(sys_mgr_base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			switch (socfpgaclk->clk_phase[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				clk_phase[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			case 45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				clk_phase[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				clk_phase[i] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			case 135:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				clk_phase[i] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				clk_phase[i] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			case 225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				clk_phase[i] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				clk_phase[i] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			case 315:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				clk_phase[i] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				clk_phase[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			hs_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct clk_ops gateclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.prepare = socfpga_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.recalc_rate = socfpga_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.get_parent = socfpga_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.set_parent = socfpga_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void __init socfpga_gate_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 clk_gate[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 div_reg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32 clk_phase[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u32 fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct socfpga_gate_clk *socfpga_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	const char *parent_name[SOCFPGA_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (WARN_ON(!socfpga_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (WARN_ON(!ops))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		clk_gate[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (clk_gate[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		socfpga_clk->hw.bit_idx = clk_gate[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ops->enable = clk_gate_ops.enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ops->disable = clk_gate_ops.disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		socfpga_clk->fixed_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		socfpga_clk->fixed_div = fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		socfpga_clk->shift = div_reg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		socfpga_clk->width = div_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		socfpga_clk->div_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		socfpga_clk->clk_phase[0] = clk_phase[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		socfpga_clk->clk_phase[1] = clk_phase[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (init.num_parents < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ops->get_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		ops->set_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	init.parent_names = parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	socfpga_clk->hw.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	clk = clk_register(NULL, &socfpga_clk->hw.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		kfree(socfpga_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (WARN_ON(rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }