^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "stratix10-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 div = 1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) if (socfpgaclk->fixed_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) div = socfpgaclk->fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) } else if (socfpgaclk->div_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) val &= GENMASK(socfpgaclk->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) div = (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 div = 1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) val &= GENMASK(socfpgaclk->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) div = (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) div = div ? 4 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 parent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (socfpgaclk->bypass_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mask = (0x1 << socfpgaclk->bypass_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) socfpgaclk->bypass_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct clk_ops gateclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .recalc_rate = socfpga_gate_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .get_parent = socfpga_gate_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct clk_ops dbgclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .recalc_rate = socfpga_dbg_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .get_parent = socfpga_gate_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct socfpga_gate_clk *socfpga_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const char *parent_name = clks->parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!socfpga_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) socfpga_clk->hw.reg = regbase + clks->gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) socfpga_clk->hw.bit_idx = clks->gate_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gateclk_ops.enable = clk_gate_ops.enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) gateclk_ops.disable = clk_gate_ops.disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) socfpga_clk->fixed_div = clks->fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (clks->div_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) socfpga_clk->div_reg = regbase + clks->div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) socfpga_clk->div_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) socfpga_clk->width = clks->div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) socfpga_clk->shift = clks->div_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (clks->bypass_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) socfpga_clk->bypass_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) socfpga_clk->bypass_shift = clks->bypass_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (streq(clks->name, "cs_pdbg_clk"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) init.ops = &dbgclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) init.ops = &gateclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) init.name = clks->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) init.flags = clks->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) init.num_parents = clks->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (init.parent_names == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) init.parent_data = clks->parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) socfpga_clk->hw.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk = clk_register(NULL, &socfpga_clk->hw.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) kfree(socfpga_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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