^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Altera Corporation. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define streq(a, b) (strcmp((a), (b)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* SDMMC Group for System Manager defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 div = 1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (socfpgaclk->fixed_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) div = socfpgaclk->fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) else if (socfpgaclk->div_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) val &= GENMASK(socfpgaclk->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) div = (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int socfpga_clk_prepare(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 hs_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 clk_phase[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) switch (socfpgaclk->clk_phase[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clk_phase[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case 45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clk_phase[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clk_phase[i] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) case 135:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk_phase[i] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clk_phase[i] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clk_phase[i] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk_phase[i] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case 315:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_phase[i] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk_phase[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regmap_write(socfpgaclk->sys_mgr_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk_ops gateclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .prepare = socfpga_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .recalc_rate = socfpga_gate_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void __init __socfpga_gate_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct clk_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 clk_gate[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 div_reg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 clk_phase[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct socfpga_gate_clk *socfpga_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const char *parent_name[SOCFPGA_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (WARN_ON(!socfpga_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk_gate[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (clk_gate[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) socfpga_clk->hw.bit_idx = clk_gate[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gateclk_ops.enable = clk_gate_ops.enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) gateclk_ops.disable = clk_gate_ops.disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) socfpga_clk->fixed_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) socfpga_clk->fixed_div = fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) socfpga_clk->shift = div_reg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) socfpga_clk->width = div_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) socfpga_clk->div_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) socfpga_clk->clk_phase[0] = clk_phase[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) socfpga_clk->clk_phase[1] = clk_phase[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) socfpga_clk->sys_mgr_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) syscon_regmap_lookup_by_compatible("altr,sys-mgr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_err("%s: failed to find altr,sys-mgr regmap!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) kfree(socfpga_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) init.parent_names = parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) socfpga_clk->hw.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk = clk_register(NULL, &socfpga_clk->hw.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) kfree(socfpga_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (WARN_ON(rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __init socfpga_a10_gate_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __socfpga_gate_init(node, &gateclk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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