^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/agilex-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "stratix10-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct clk_parent_data pll_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct clk_parent_data boot_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct clk_parent_data mpu_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { .fw_name = "main_pll_c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = "main_pll_c0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { .fw_name = "peri_pll_c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .name = "peri_pll_c0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct clk_parent_data noc_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .fw_name = "main_pll_c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .name = "main_pll_c1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .fw_name = "peri_pll_c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "peri_pll_c1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct clk_parent_data emaca_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .fw_name = "main_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "main_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .fw_name = "peri_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "peri_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct clk_parent_data emacb_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .fw_name = "main_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "main_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .fw_name = "peri_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "peri_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct clk_parent_data emac_ptp_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .fw_name = "main_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .name = "main_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .fw_name = "peri_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "peri_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct clk_parent_data gpio_db_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .fw_name = "main_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "main_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .fw_name = "peri_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "peri_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct clk_parent_data psi_ref_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .fw_name = "main_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "main_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .fw_name = "peri_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "peri_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct clk_parent_data sdmmc_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .fw_name = "main_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "main_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .fw_name = "peri_pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "peri_pll_c3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct clk_parent_data s2f_usr0_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .fw_name = "main_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "main_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .fw_name = "peri_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "peri_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct clk_parent_data s2f_usr1_free_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .fw_name = "main_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "main_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .fw_name = "peri_pll_c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .name = "peri_pll_c2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .fw_name = "osc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "osc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .fw_name = "cb-intosc-hs-div2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "cb-intosc-hs-div2-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .fw_name = "f2s-free-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "f2s-free-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct clk_parent_data mpu_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .fw_name = "mpu_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .name = "mpu_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct clk_parent_data emac_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .fw_name = "emaca_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "emaca_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .fw_name = "emacb_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "emacb_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct clk_parent_data noc_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .fw_name = "noc_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "noc_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct clk_parent_data sdmmc_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .fw_name = "sdmmc_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "sdmmc_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct clk_parent_data s2f_user0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .fw_name = "s2f_user0_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "s2f_user0_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct clk_parent_data s2f_user1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .fw_name = "s2f_user1_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .name = "s2f_user1_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct clk_parent_data psi_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .fw_name = "psi_ref_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "psi_ref_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct clk_parent_data gpio_db_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .fw_name = "gpio_db_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .name = "gpio_db_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct clk_parent_data emac_ptp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .fw_name = "emac_ptp_free_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = "emac_ptp_free_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .fw_name = "boot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "boot_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* clocks in AO (always on) controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct stratix10_pll_clock agilex_pll_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0, 0x3C, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0, 0x40, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0, 4, 0x30, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0, 0xD4, 0, 0x88, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0, 0xD8, 0, 0x88, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct stratix10_gate_clock agilex_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0, 0, 0, 0, 0x30, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0, 0, 0, 0, 0, 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0, 0, 0, 0, 0, 0, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 1, 0x44, 0, 2, 0x30, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 2, 0x44, 8, 2, 0x30, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * being the SP timers, thus cannot get gated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 3, 0x44, 16, 2, 0x30, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 4, 0x44, 24, 2, 0x30, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 4, 0x44, 26, 2, 0x30, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 4, 0x44, 28, 1, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 5, 0, 0, 0, 0x30, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0, 0, 0, 0, 0x94, 26, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 1, 0, 0, 0, 0x94, 27, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 2, 0, 0, 0, 0x94, 28, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 3, 0, 0, 0, 0x88, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { AGILEX_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 4, 0x98, 0, 16, 0x88, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 5, 0, 0, 0, 0x88, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 6, 0, 0, 0, 0x30, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 6, 0, 0, 0, 0x88, 5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 7, 0, 0, 0, 0x88, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 8, 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 9, 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 10, 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 10, 0, 0, 0, 0, 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 10, 0, 0, 0, 0, 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int nums, struct stratix10_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clk = s10_register_periph(&clks[i], base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int nums, struct stratix10_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) clk = s10_register_cnt_periph(&clks[i], base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) clk = s10_register_gate(&clks[i], base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int nums, struct stratix10_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk = agilex_register_pll(&clks[i], base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int nr_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct stratix10_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct clk **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ERR_CAST(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk_data->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!clk_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_data->clk_data.clks = clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk_data->clk_data.clk_num = nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int agilex_clkmgr_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct stratix10_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (IS_ERR(clk_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return PTR_ERR(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) agilex_clk_register_c_perip(agilex_main_perip_c_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ARRAY_SIZE(agilex_main_perip_cnt_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct of_device_id agilex_clkmgr_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { .compatible = "intel,agilex-clkmgr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .data = agilex_clkmgr_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct platform_driver agilex_clkmgr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .probe = agilex_clkmgr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .name = "agilex-clkmgr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .of_match_table = agilex_clkmgr_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int __init agilex_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return platform_driver_register(&agilex_clkmgr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) core_initcall(agilex_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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