^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * common clks module for all SiRF SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define KHZ 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MHZ (KHZ * KHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static void __iomem *sirfsoc_clk_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static void __iomem *sirfsoc_rsc_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * SiRFprimaII clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - 2 oscillators: osc-26MHz, rtc-32.768KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - 3 standard configurable plls: pll1, pll2 & pll3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - 2 exclusive plls: usb phy pll and sata phy pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * display and sdphy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Each clock domain can select its own clock source from five clock sources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * clock of the group clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - dsp domain: gps, mf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - sys domain: security
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned short regofs; /* register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk_dmn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) signed char enable_bit; /* enable bit: 0 ~ 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned short regofs; /* register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk_std {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) signed char enable_bit; /* enable bit: 0 ~ 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int std_clk_is_enabled(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int std_clk_enable(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void std_clk_disable(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline unsigned long clkc_readl(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return readl(sirfsoc_clk_vbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void clkc_writel(u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(val, sirfsoc_clk_vbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * std pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long fin = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_pll *clk = to_pllclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SIRFSOC_CLKC_PLL1_CFG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (clkc_readl(regcfg2) & BIT(2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* pll bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* fout = fin * nf / nr / od */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 cfg0 = clkc_readl(clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) WARN_ON(fin % MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return fin / MHZ * nf / nr / od * MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long fin, nf, nr, od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u64 dividend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * fout = fin * nf / (nr * od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * set od = 1, nr = fin/MHz, so fout = nf * MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rate = rate - rate % MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) nf = rate / MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (nf > BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) nf = BIT(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (nf < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) nf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) fin = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) nr = fin / MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (nr > BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) nr = BIT(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) od = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dividend = (u64)fin * nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) do_div(dividend, nr * od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return (long)dividend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_pll *clk = to_pllclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long fin, nf, nr, od, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * fout = fin * nf / (nr * od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * set od = 1, nr = fin/MHz, so fout = nf * MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) nf = rate / MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) fin = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) BUG_ON(fin < MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) nr = fin / MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BUG_ON((fin % MHZ) || nr > BIT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) od = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clkc_writel(reg, clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clkc_writel((nf >> 1) - 1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while (!(clkc_readl(reg) & BIT(6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * SiRF SoC has not cpu clock control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * So bypass to it's parent pll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk_hw *parent_clk = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * SiRF SoC has not cpu clock control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * So return the parent pll rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk_hw *parent_clk = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return clk_hw_get_rate(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct clk_ops std_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .recalc_rate = pll_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .round_rate = pll_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .set_rate = pll_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const char * const pll_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct clk_init_data clk_pll1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ops = &std_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct clk_init_data clk_pll2_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ops = &std_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct clk_init_data clk_pll3_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .ops = &std_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct clk_pll clk_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .regofs = SIRFSOC_CLKC_PLL1_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .init = &clk_pll1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct clk_pll clk_pll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .regofs = SIRFSOC_CLKC_PLL2_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .init = &clk_pll2_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct clk_pll clk_pll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .regofs = SIRFSOC_CLKC_PLL3_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .init = &clk_pll3_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * usb uses specified pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int usb_pll_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SIRFSOC_USBPHY_PLL_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void usb_pll_clk_disable(struct clk_hw *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct clk_ops usb_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .enable = usb_pll_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .disable = usb_pll_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .recalc_rate = usb_pll_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct clk_init_data clk_usb_pll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "usb_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .ops = &usb_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct clk_hw usb_pll_clk_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .init = &clk_usb_pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * clock domains - cpu, mem, sys/io, dsp, gfx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const char * const dmn_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static u8 dmn_clk_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct clk_dmn *clk = to_dmnclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 cfg = clkc_readl(clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) const char *name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* parent of io domain can only be pll3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (strcmp(name, "io") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) WARN_ON((cfg & (BIT(3) - 1)) > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return cfg & (BIT(3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct clk_dmn *clk = to_dmnclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 cfg = clkc_readl(clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const char *name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* parent of io domain can only be pll3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (strcmp(name, "io") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cfg &= ~(BIT(3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clkc_writel(cfg | parent, clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* BIT(3) - switching status: 1 - busy, 0 - done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while (clkc_readl(clk->regofs) & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long fin = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct clk_dmn *clk = to_dmnclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 cfg = clkc_readl(clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (cfg & BIT(24)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* fcd bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * wait count: bit[19:16], hold count: bit[23:20]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 wait = (cfg >> 16) & (BIT(4) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 hold = (cfg >> 20) & (BIT(4) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return fin / (wait + hold + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned ratio, wait, hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const char *name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) fin = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ratio = fin / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ratio < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ratio = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ratio > BIT(bits + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ratio = BIT(bits + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) wait = (ratio >> 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hold = ratio - wait - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return fin / (wait + hold + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct clk_dmn *clk = to_dmnclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned ratio, wait, hold, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const char *name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fin = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ratio = fin / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) WARN_ON(fin % rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) wait = (ratio >> 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hold = ratio - wait - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) reg = clkc_readl(clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) reg |= (wait << 16) | (hold << 20) | BIT(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clkc_writel(reg, clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* waiting FCD been effective */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) while (clkc_readl(clk->regofs) & BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret1, ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct clk *cur_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (rate == clk_get_rate(clk_pll1.hw.clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (rate == clk_get_rate(clk_pll2.hw.clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (rate == clk_get_rate(clk_pll3.hw.clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cur_parent = clk_get_parent(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* switch to tmp pll before setting parent clock's rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (cur_parent == clk_pll1.hw.clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BUG_ON(ret1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret2 ? ret2 : ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct clk_ops msi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .set_rate = dmn_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .round_rate = dmn_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .recalc_rate = dmn_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .set_parent = dmn_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .get_parent = dmn_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct clk_init_data clk_mem_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .ops = &msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct clk_dmn clk_mem = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .regofs = SIRFSOC_CLKC_MEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .init = &clk_mem_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct clk_init_data clk_sys_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .ops = &msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct clk_dmn clk_sys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .regofs = SIRFSOC_CLKC_SYS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .init = &clk_sys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct clk_init_data clk_io_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .name = "io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .ops = &msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct clk_dmn clk_io = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .regofs = SIRFSOC_CLKC_IO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .init = &clk_io_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct clk_ops cpu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .set_parent = dmn_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .get_parent = dmn_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .set_rate = cpu_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .round_rate = cpu_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .recalc_rate = cpu_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct clk_init_data clk_cpu_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .ops = &cpu_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct clk_dmn clk_cpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .regofs = SIRFSOC_CLKC_CPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .init = &clk_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct clk_ops dmn_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .is_enabled = std_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .enable = std_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .disable = std_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .set_rate = dmn_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .round_rate = dmn_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .recalc_rate = dmn_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .set_parent = dmn_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .get_parent = dmn_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* dsp, gfx, mm, lcd and vpp domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct clk_init_data clk_dsp_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "dsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct clk_dmn clk_dsp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .regofs = SIRFSOC_CLKC_DSP_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .init = &clk_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct clk_init_data clk_gfx_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "gfx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct clk_dmn clk_gfx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .regofs = SIRFSOC_CLKC_GFX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .enable_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .init = &clk_gfx_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct clk_init_data clk_mm_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = "mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct clk_dmn clk_mm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .regofs = SIRFSOC_CLKC_MM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .enable_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .init = &clk_mm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * for atlas6, gfx2d holds the bit of prima2's clk_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define clk_gfx2d clk_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct clk_init_data clk_lcd_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .name = "lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct clk_dmn clk_lcd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .regofs = SIRFSOC_CLKC_LCD_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .enable_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .init = &clk_lcd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct clk_init_data clk_vpp_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .name = "vpp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct clk_dmn clk_vpp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .regofs = SIRFSOC_CLKC_LCD_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .enable_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .init = &clk_vpp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct clk_init_data clk_mmc01_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "mmc01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct clk_init_data clk_mmc23_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "mmc23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct clk_init_data clk_mmc45_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .name = "mmc45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .ops = &dmn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .parent_names = dmn_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .num_parents = ARRAY_SIZE(dmn_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * peripheral controllers in io domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int std_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct clk_std *clk = to_stdclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bit = clk->enable_bit % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) reg = clk->enable_bit / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return !!(clkc_readl(reg) & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int std_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct clk_std *clk = to_stdclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) bit = clk->enable_bit % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) reg = clk->enable_bit / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) val = clkc_readl(reg) | BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clkc_writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void std_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct clk_std *clk = to_stdclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) bit = clk->enable_bit % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) reg = clk->enable_bit / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) val = clkc_readl(reg) & ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) clkc_writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const char * const std_clk_io_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct clk_ops ios_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .is_enabled = std_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .enable = std_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .disable = std_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct clk_init_data clk_cphif_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = "cphif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static struct clk_std clk_cphif = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .enable_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .init = &clk_cphif_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const struct clk_init_data clk_dmac0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .name = "dmac0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static struct clk_std clk_dmac0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .enable_bit = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .init = &clk_dmac0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const struct clk_init_data clk_dmac1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .name = "dmac1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static struct clk_std clk_dmac1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .enable_bit = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .init = &clk_dmac1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const struct clk_init_data clk_audio_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct clk_std clk_audio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .enable_bit = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .init = &clk_audio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct clk_init_data clk_uart0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .name = "uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct clk_std clk_uart0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .enable_bit = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .init = &clk_uart0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const struct clk_init_data clk_uart1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static struct clk_std clk_uart1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .enable_bit = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .init = &clk_uart1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct clk_init_data clk_uart2_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = "uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct clk_std clk_uart2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .enable_bit = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .init = &clk_uart2_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const struct clk_init_data clk_usp0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "usp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static struct clk_std clk_usp0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .enable_bit = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .init = &clk_usp0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct clk_init_data clk_usp1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .name = "usp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct clk_std clk_usp1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .enable_bit = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .init = &clk_usp1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct clk_init_data clk_usp2_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "usp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct clk_std clk_usp2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .enable_bit = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .init = &clk_usp2_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct clk_init_data clk_vip_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .name = "vip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static struct clk_std clk_vip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .enable_bit = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .init = &clk_vip_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const struct clk_init_data clk_spi0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .name = "spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static struct clk_std clk_spi0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .enable_bit = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .init = &clk_spi0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct clk_init_data clk_spi1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .name = "spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static struct clk_std clk_spi1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .enable_bit = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .init = &clk_spi1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct clk_init_data clk_tsc_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "tsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct clk_std clk_tsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .enable_bit = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .init = &clk_tsc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const struct clk_init_data clk_i2c0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static struct clk_std clk_i2c0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .enable_bit = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .init = &clk_i2c0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static const struct clk_init_data clk_i2c1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static struct clk_std clk_i2c1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .enable_bit = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .init = &clk_i2c1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct clk_init_data clk_pwmc_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "pwmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static struct clk_std clk_pwmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .enable_bit = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .init = &clk_pwmc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const struct clk_init_data clk_efuse_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .name = "efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static struct clk_std clk_efuse = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .enable_bit = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .init = &clk_efuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const struct clk_init_data clk_pulse_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = "pulse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static struct clk_std clk_pulse = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .enable_bit = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .init = &clk_pulse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const char * const std_clk_dsp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "dsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const struct clk_init_data clk_gps_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .name = "gps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .parent_names = std_clk_dsp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static struct clk_std clk_gps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .enable_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .init = &clk_gps_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const struct clk_init_data clk_mf_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = "mf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .parent_names = std_clk_io_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .num_parents = ARRAY_SIZE(std_clk_io_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static struct clk_std clk_mf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .enable_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .init = &clk_mf_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const char * const std_clk_sys_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const struct clk_init_data clk_security_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .name = "security",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .parent_names = std_clk_sys_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .num_parents = ARRAY_SIZE(std_clk_sys_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static struct clk_std clk_security = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .enable_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .init = &clk_security_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const char * const std_clk_usb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "usb_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const struct clk_init_data clk_usb0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .name = "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .parent_names = std_clk_usb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .num_parents = ARRAY_SIZE(std_clk_usb_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct clk_std clk_usb0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .enable_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .init = &clk_usb0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const struct clk_init_data clk_usb1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .name = "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .ops = &ios_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .parent_names = std_clk_usb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .num_parents = ARRAY_SIZE(std_clk_usb_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static struct clk_std clk_usb1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .enable_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .init = &clk_usb1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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