^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock tree for CSR SiRFAtlas7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SIRFSOC_CLKC_MEMPLL_AB_FREQ 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SIRFSOC_CLKC_MEMPLL_AB_SSC 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIRFSOC_CLKC_MEMPLL_AB_CTRL0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIRFSOC_CLKC_MEMPLL_AB_CTRL1 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIRFSOC_CLKC_MEMPLL_AB_STATUS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIRFSOC_CLKC_CPUPLL_AB_FREQ 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIRFSOC_CLKC_CPUPLL_AB_SSC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIRFSOC_CLKC_CPUPLL_AB_CTRL0 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_CLKC_CPUPLL_AB_CTRL1 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIRFSOC_CLKC_CPUPLL_AB_STATUS 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIRFSOC_CLKC_SYS0PLL_AB_FREQ 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIRFSOC_CLKC_SYS0PLL_AB_SSC 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIRFSOC_CLKC_SYS0PLL_AB_STATUS 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIRFSOC_CLKC_SYS1PLL_AB_FREQ 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIRFSOC_CLKC_SYS1PLL_AB_SSC 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIRFSOC_CLKC_SYS1PLL_AB_STATUS 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SIRFSOC_CLKC_SYS2PLL_AB_FREQ 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SIRFSOC_CLKC_SYS2PLL_AB_SSC 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SIRFSOC_CLKC_SYS2PLL_AB_STATUS 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SIRFSOC_CLKC_SYS3PLL_AB_FREQ 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIRFSOC_CLKC_SYS3PLL_AB_SSC 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SIRFSOC_CLKC_SYS3PLL_AB_STATUS 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIRFSOC_ABPLL_CTRL0_SSEN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SIRFSOC_ABPLL_CTRL0_BYPASS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SIRFSOC_ABPLL_CTRL0_RESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIRFSOC_CLKC_AUDIO_DTO_INC 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SIRFSOC_CLKC_DISP0_DTO_INC 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SIRFSOC_CLKC_DISP1_DTO_INC 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SIRFSOC_CLKC_AUDIO_DTO_SRC 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SIRFSOC_CLKC_AUDIO_DTO_ENA 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SIRFSOC_CLKC_AUDIO_DTO_DROFF 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIRFSOC_CLKC_DISP0_DTO_SRC 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SIRFSOC_CLKC_DISP0_DTO_ENA 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SIRFSOC_CLKC_DISP0_DTO_DROFF 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SIRFSOC_CLKC_DISP1_DTO_SRC 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SIRFSOC_CLKC_DISP1_DTO_ENA 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SIRFSOC_CLKC_DISP1_DTO_DROFF 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SIRFSOC_CLKC_I2S_CLK_SEL 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SIRFSOC_CLKC_I2S_SEL_STAT 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SIRFSOC_CLKC_USBPHY_CLK_SEL 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SIRFSOC_CLKC_BTSS_CLKDIV_CFG 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SIRFSOC_CLKC_BTSS_CLKDIV_ENA 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SIRFSOC_CLKC_BTSS_CLK_SEL 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SIRFSOC_CLKC_RGMII_CLKDIV_CFG 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SIRFSOC_CLKC_RGMII_CLKDIV_ENA 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SIRFSOC_CLKC_RGMII_CLK_SEL 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SIRFSOC_CLKC_CPU_CLKDIV_CFG 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SIRFSOC_CLKC_CPU_CLKDIV_ENA 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SIRFSOC_CLKC_CPU_CLK_SEL 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SIRFSOC_CLKC_CPU_CLK_SEL_STAT 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SIRFSOC_CLKC_SDPHY01_CLK_SEL 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SIRFSOC_CLKC_SDPHY23_CLK_SEL 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SIRFSOC_CLKC_SDPHY45_CLK_SEL 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SIRFSOC_CLKC_SDPHY67_CLK_SEL 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SIRFSOC_CLKC_CAN_CLKDIV_CFG 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SIRFSOC_CLKC_CAN_CLKDIV_ENA 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SIRFSOC_CLKC_CAN_CLK_SEL 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SIRFSOC_CLKC_CAN_CLK_SEL_STAT 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SIRFSOC_CLKC_DEINT_CLKDIV_CFG 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SIRFSOC_CLKC_DEINT_CLKDIV_ENA 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SIRFSOC_CLKC_DEINT_CLK_SEL 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SIRFSOC_CLKC_NAND_CLKDIV_CFG 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SIRFSOC_CLKC_NAND_CLKDIV_ENA 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SIRFSOC_CLKC_NAND_CLK_SEL 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SIRFSOC_CLKC_NAND_CLK_SEL_STAT 0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SIRFSOC_CLKC_DISP0_CLKDIV_CFG 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SIRFSOC_CLKC_DISP0_CLKDIV_ENA 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SIRFSOC_CLKC_DISP0_CLK_SEL 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT 0x017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SIRFSOC_CLKC_DISP1_CLKDIV_CFG 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SIRFSOC_CLKC_DISP1_CLKDIV_ENA 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SIRFSOC_CLKC_DISP1_CLK_SEL 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT 0x018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SIRFSOC_CLKC_GPU_CLKDIV_CFG 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SIRFSOC_CLKC_GPU_CLKDIV_ENA 0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SIRFSOC_CLKC_GPU_CLK_SEL 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SIRFSOC_CLKC_GPU_CLK_SEL_STAT 0x019c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SIRFSOC_CLKC_GNSS_CLKDIV_CFG 0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SIRFSOC_CLKC_GNSS_CLKDIV_ENA 0x01a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SIRFSOC_CLKC_GNSS_CLK_SEL 0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT 0x01ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0 0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1 0x01b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SIRFSOC_CLKC_SHARED_DIVIDER_ENA 0x01b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SIRFSOC_CLKC_SYS_CLK_SEL 0x01bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SIRFSOC_CLKC_SYS_CLK_SEL_STAT 0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SIRFSOC_CLKC_IO_CLK_SEL 0x01c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SIRFSOC_CLKC_IO_CLK_SEL_STAT 0x01c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SIRFSOC_CLKC_G2D_CLK_SEL 0x01cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SIRFSOC_CLKC_G2D_CLK_SEL_STAT 0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SIRFSOC_CLKC_JPENC_CLK_SEL 0x01d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT 0x01d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SIRFSOC_CLKC_VDEC_CLK_SEL 0x01dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SIRFSOC_CLKC_GMAC_CLK_SEL 0x01e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT 0x01e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SIRFSOC_CLKC_USB_CLK_SEL 0x01ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SIRFSOC_CLKC_USB_CLK_SEL_STAT 0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SIRFSOC_CLKC_KAS_CLK_SEL 0x01f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SIRFSOC_CLKC_KAS_CLK_SEL_STAT 0x01f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SIRFSOC_CLKC_SEC_CLK_SEL 0x01fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SIRFSOC_CLKC_SEC_CLK_SEL_STAT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SIRFSOC_CLKC_SDR_CLK_SEL 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SIRFSOC_CLKC_SDR_CLK_SEL_STAT 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SIRFSOC_CLKC_VIP_CLK_SEL 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SIRFSOC_CLKC_VIP_CLK_SEL_STAT 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SIRFSOC_CLKC_NOCD_CLK_SEL 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SIRFSOC_CLKC_NOCR_CLK_SEL 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SIRFSOC_CLKC_TPIU_CLK_SEL 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SIRFSOC_CLKC_ROOT_CLK_EN0_SET 0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SIRFSOC_CLKC_ROOT_CLK_EN1_SET 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR 0x023c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SIRFSOC_CLKC_LEAF_CLK_EN0_SET 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT 0x024c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SIRFSOC_CLKC_RSTC_A7_SW_RST 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SIRFSOC_CLKC_LEAF_CLK_EN1_SET 0x04a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SIRFSOC_CLKC_LEAF_CLK_EN2_SET 0x04b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SIRFSOC_CLKC_LEAF_CLK_EN3_SET 0x04d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SIRFSOC_CLKC_LEAF_CLK_EN4_SET 0x04e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SIRFSOC_CLKC_LEAF_CLK_EN5_SET 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SIRFSOC_CLKC_LEAF_CLK_EN6_SET 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SIRFSOC_CLKC_LEAF_CLK_EN7_SET 0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SIRFSOC_CLKC_LEAF_CLK_EN8_SET 0x0548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SIRFSOC_NOC_CLK_IDLEREQ_SET 0x02D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SIRFSOC_NOC_CLK_IDLEREQ_CLR 0x02D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SIRFSOC_NOC_CLK_SLVRDY_SET 0x02E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SIRFSOC_NOC_CLK_SLVRDY_CLR 0x02EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SIRFSOC_NOC_CLK_IDLE_STATUS 0x02F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u16 regofs; /* register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct clk_dto {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 inc_offset; /* dto increment offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 src_offset; /* dto src offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum clk_unit_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CLK_UNIT_NOC_OTHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CLK_UNIT_NOC_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CLK_UNIT_NOC_SOCKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct clk_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 regofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 idle_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct atlas7_div_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const char *div_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const char *gate_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 divider_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 div_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 gate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 gate_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct atlas7_mux_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const char *mux_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 parent_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 mux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct atlas7_unit_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const char *unit_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 regofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 idle_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct atlas7_reset_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 clk_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 clk_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 rst_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 rst_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void __iomem *sirfsoc_clk_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct clk_div_table pll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .val = 4, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { .val = 5, .div = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static DEFINE_SPINLOCK(cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static DEFINE_SPINLOCK(mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static DEFINE_SPINLOCK(sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static DEFINE_SPINLOCK(sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static DEFINE_SPINLOCK(sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static DEFINE_SPINLOCK(sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static DEFINE_SPINLOCK(usbphy_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static DEFINE_SPINLOCK(btss_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static DEFINE_SPINLOCK(rgmii_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static DEFINE_SPINLOCK(cpu_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static DEFINE_SPINLOCK(sdphy01_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static DEFINE_SPINLOCK(sdphy23_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static DEFINE_SPINLOCK(sdphy45_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static DEFINE_SPINLOCK(sdphy67_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static DEFINE_SPINLOCK(can_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static DEFINE_SPINLOCK(deint_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static DEFINE_SPINLOCK(nand_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static DEFINE_SPINLOCK(disp0_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static DEFINE_SPINLOCK(disp1_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static DEFINE_SPINLOCK(gpu_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static DEFINE_SPINLOCK(gnss_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* gate register shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static DEFINE_SPINLOCK(share_div_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static DEFINE_SPINLOCK(root0_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static DEFINE_SPINLOCK(root1_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static DEFINE_SPINLOCK(leaf0_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static DEFINE_SPINLOCK(leaf1_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static DEFINE_SPINLOCK(leaf2_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static DEFINE_SPINLOCK(leaf3_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static DEFINE_SPINLOCK(leaf4_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static DEFINE_SPINLOCK(leaf5_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static DEFINE_SPINLOCK(leaf6_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static DEFINE_SPINLOCK(leaf7_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static DEFINE_SPINLOCK(leaf8_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline unsigned long clkc_readl(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return readl(sirfsoc_clk_vbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static inline void clkc_writel(u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(val, sirfsoc_clk_vbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * ABPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * integer mode: Fvco = Fin * 2 * NF / NR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Spread Spectrum mode: Fvco = Fin * SSN / NR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * SSN = 2^24 / (256 * ((ssdiv >> ssdepth) << ssdepth) + (ssmod << ssdepth))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long fin = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct clk_pll *clk = to_pllclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SIRFSOC_CLKC_MEMPLL_AB_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 regfreq = clkc_readl(clk->regofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SIRFSOC_CLKC_MEMPLL_AB_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 nr = (regfreq >> 16 & (BIT(3) - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 nf = (regfreq & (BIT(9) - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 ssdiv = regssc >> 8 & (BIT(12) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 ssdepth = regssc >> 20 & (BIT(2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 ssmod = regssc & (BIT(8) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rate = fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rate *= 1 << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) do_div(rate, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) + (ssmod << ssdepth)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rate = 2 * fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rate *= nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) do_div(rate, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct clk_ops ab_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .recalc_rate = pll_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const char * const pll_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct clk_init_data clk_cpupll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "cpupll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .ops = &ab_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct clk_pll clk_cpupll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .init = &clk_cpupll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct clk_init_data clk_mempll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .name = "mempll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ops = &ab_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk_pll clk_mempll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .init = &clk_mempll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct clk_init_data clk_sys0pll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "sys0pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .ops = &ab_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct clk_pll clk_sys0pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .init = &clk_sys0pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct clk_init_data clk_sys1pll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .name = "sys1pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .ops = &ab_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct clk_pll clk_sys1pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .init = &clk_sys1pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct clk_init_data clk_sys2pll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = "sys2pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .ops = &ab_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct clk_pll clk_sys2pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .init = &clk_sys2pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct clk_init_data clk_sys3pll_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .name = "sys3pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .ops = &ab_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .parent_names = pll_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .num_parents = ARRAY_SIZE(pll_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct clk_pll clk_sys3pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .init = &clk_sys3pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * DTO in clkc, default enable double resolution mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * double resolution mode:fout = fin * finc / 2^29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * normal mode:fout = fin * finc / 2^28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DTO_RESL_DOUBLE (1ULL << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DTO_RESL_NORMAL (1ULL << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int dto_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return !!(clkc_readl(reg) & BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int dto_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) val = clkc_readl(reg) | BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) clkc_writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void dto_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val = clkc_readl(reg) & ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clkc_writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u64 rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 finc = clkc_readl(clk->inc_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) rate *= finc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (droff & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Double resolution off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) do_div(rate, DTO_RESL_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) do_div(rate, DTO_RESL_DOUBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u64 dividend = rate * DTO_RESL_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) do_div(dividend, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dividend *= *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) do_div(dividend, DTO_RESL_DOUBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return dividend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u64 dividend = rate * DTO_RESL_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) do_div(dividend, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clkc_writel(dividend, clk->inc_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static u8 dto_clk_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return clkc_readl(clk->src_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * dto need CLK_SET_PARENT_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int dto_clk_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct clk_dto *clk = to_dtoclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) clkc_writel(index, clk->src_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct clk_ops dto_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .is_enabled = dto_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .enable = dto_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .disable = dto_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .recalc_rate = dto_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .round_rate = dto_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .set_rate = dto_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .get_parent = dto_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .set_parent = dto_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* dto parent clock as syspllvco/clk1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const char * const audiodto_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "sys0pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "sys1pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "sys3pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct clk_init_data clk_audiodto_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "audio_dto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .ops = &dto_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .parent_names = audiodto_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .num_parents = ARRAY_SIZE(audiodto_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct clk_dto clk_audio_dto = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .init = &clk_audiodto_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const char * const disp0dto_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "sys0pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "sys1pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "sys3pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const struct clk_init_data clk_disp0dto_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "disp0_dto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .ops = &dto_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .parent_names = disp0dto_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_parents = ARRAY_SIZE(disp0dto_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct clk_dto clk_disp0_dto = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .init = &clk_disp0dto_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const disp1dto_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "sys0pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "sys1pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "sys3pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct clk_init_data clk_disp1dto_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .name = "disp1_dto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .ops = &dto_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .parent_names = disp1dto_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .num_parents = ARRAY_SIZE(disp1dto_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static struct clk_dto clk_disp1_dto = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .init = &clk_disp1dto_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static struct atlas7_div_init_data divider_list[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const char * const i2s_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "audio_dto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* "pwm_i2s01" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const char * const usbphy_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "sys0pll_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "sys1pll_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "sys2pll_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "sys3pll_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const char * const btss_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "sys0pll_a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "sys1pll_a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "sys2pll_a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "sys3pll_a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char * const rgmii_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "sys0pll_a3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "sys1pll_a3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "sys2pll_a3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "sys3pll_a3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const char * const cpu_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "sys0pll_a4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "sys1pll_a4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "cpupll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const char * const sdphy01_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "sys0pll_a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "sys1pll_a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "sys2pll_a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "sys3pll_a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const char * const sdphy23_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "sys0pll_a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "sys1pll_a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "sys2pll_a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "sys3pll_a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const char * const sdphy45_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "sys0pll_a7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "sys1pll_a7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "sys2pll_a7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "sys3pll_a7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const char * const sdphy67_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "sys0pll_a8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "sys1pll_a8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "sys2pll_a8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "sys3pll_a8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const char * const can_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "sys0pll_a9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "sys1pll_a9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "sys2pll_a9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "sys3pll_a9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const char * const deint_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "sys0pll_a10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "sys1pll_a10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "sys2pll_a10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "sys3pll_a10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const char * const nand_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "sys0pll_a11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "sys1pll_a11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "sys2pll_a11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "sys3pll_a11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const char * const disp0_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "sys0pll_a12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "sys1pll_a12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "sys2pll_a12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "sys3pll_a12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "disp0_dto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const char * const disp1_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "sys0pll_a13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "sys1pll_a13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "sys2pll_a13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "sys3pll_a13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "disp1_dto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const char * const gpu_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "sys0pll_a14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "sys1pll_a14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "sys2pll_a14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "sys3pll_a14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const char * const gnss_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "sys0pll_a15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "sys1pll_a15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "sys2pll_a15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) "sys3pll_a15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const char * const sys_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static const char * const io_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const char * const g2d_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const char * const jpenc_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static const char * const vdec_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const char * const gmac_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const char * const usb_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const char * const kas_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const char * const sec_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const char * const sdr_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const char * const vip_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const char * const nocd_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const char * const nocr_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const char * const tpiu_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) "sys2pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "sys1pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "sys1pll_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "sys1pll_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) "sys0pll_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "sys1pll_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static struct atlas7_mux_init_data mux_list[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* mux_name, parent_names, parent_num, flags, mux_flags, mux_offset, shift, width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* new unit should add start from the tail of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static struct atlas7_unit_init_data unit_list[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* unit_name, parent_name, flags, regofs, bit, lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, 0, 0, &root0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, CLK_UNIT_NOC_CLOCK, 4, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, CLK_UNIT_NOC_SOCKET, 7, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, CLK_UNIT_NOC_SOCKET, 8, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, CLK_UNIT_NOC_SOCKET, 4, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, CLK_UNIT_NOC_SOCKET, 5, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, CLK_UNIT_NOC_SOCKET, 6, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, CLK_UNIT_NOC_SOCKET, 1, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, CLK_UNIT_NOC_SOCKET, 2, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, CLK_UNIT_NOC_SOCKET, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, 0, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, CLK_UNIT_NOC_CLOCK, 20, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, CLK_UNIT_NOC_CLOCK, 21, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, CLK_UNIT_NOC_CLOCK, 22, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, CLK_UNIT_NOC_CLOCK, 18, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, CLK_UNIT_NOC_CLOCK, 23, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, CLK_UNIT_NOC_CLOCK, 19, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, CLK_UNIT_NOC_CLOCK, 17, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, 0, 0, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, 0, 0, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, CLK_UNIT_NOC_CLOCK, 10, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, CLK_UNIT_NOC_SOCKET, 14, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, CLK_UNIT_NOC_SOCKET, 11, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, CLK_UNIT_NOC_SOCKET, 13, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, CLK_UNIT_NOC_SOCKET, 15, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, CLK_UNIT_NOC_SOCKET, 16, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, CLK_UNIT_NOC_SOCKET, 17, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, CLK_UNIT_NOC_SOCKET, 18, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, CLK_UNIT_NOC_SOCKET, 12, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, 0, 0, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, CLK_UNIT_NOC_CLOCK, 7, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, CLK_UNIT_NOC_CLOCK, 9, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) { 99, "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, CLK_UNIT_NOC_CLOCK, 8, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, 0, 0, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, 0, 0, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, CLK_UNIT_NOC_CLOCK, 3, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, CLK_UNIT_NOC_CLOCK, 1, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, CLK_UNIT_NOC_CLOCK, 12, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, CLK_UNIT_NOC_SOCKET, 21, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, CLK_UNIT_NOC_SOCKET, 20, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, CLK_UNIT_NOC_SOCKET, 19, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, 0, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, 0, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, CLK_UNIT_NOC_CLOCK, 13, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, 0, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, CLK_UNIT_NOC_CLOCK, 14, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, CLK_UNIT_NOC_CLOCK, 15, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, CLK_UNIT_NOC_CLOCK, 16, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, 0, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, 0, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, 0, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, 0, 0, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, 0, 0, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, 0, 0, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, 0, 0, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, CLK_UNIT_NOC_SOCKET, 9, &leaf6_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, CLK_UNIT_NOC_SOCKET, 10, &leaf6_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, 0, 0, &leaf6_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) { 125, "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, 0, 0, &leaf6_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, CLK_UNIT_NOC_CLOCK, 0, &leaf7_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, CLK_UNIT_NOC_CLOCK, 11, &leaf7_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, 0, 0, &leaf7_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) { 130, "dmac4_io", "a7ca_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) { 131, "uart6_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) { 132, "usp3_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) { 133, "a7ca_io", "noc_btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, 0, 0, &root1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, 0, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) { 138, "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, 0, 0, &leaf0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) { 139, "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, 0, 0, &leaf0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) { 140, "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, 0, 0, &leaf0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, 0, 0, &leaf0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static int unit_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct clk_unit *clk = to_unitclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return !!(clkc_readl(reg) & BIT(clk->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int unit_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct clk_unit *clk = to_unitclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) reg = clk->regofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) spin_lock_irqsave(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) clkc_writel(BIT(clk->bit), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (clk->type == CLK_UNIT_NOC_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) else if (clk->type == CLK_UNIT_NOC_SOCKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) spin_unlock_irqrestore(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static void unit_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct clk_unit *clk = to_unitclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) spin_lock_irqsave(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (clk->type == CLK_UNIT_NOC_CLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) while (!(clkc_readl(SIRFSOC_NOC_CLK_IDLE_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) BIT(clk->idle_bit)) && (i++ < 100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (i == 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) pr_err("unit NoC Clock disconnect Error:timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /*once timeout, undo idlereq by CLR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) } else if (clk->type == CLK_UNIT_NOC_SOCKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) clkc_writel(BIT(clk->bit), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) spin_unlock_irqrestore(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const struct clk_ops unit_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .is_enabled = unit_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .enable = unit_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .disable = unit_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static struct clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) atlas7_unit_clk_register(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) const char * const parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u32 regofs, u8 bit, u32 type, u8 idle_bit, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct clk_unit *unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) unit = kzalloc(sizeof(*unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (!unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) init.ops = &unit_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) unit->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) unit->regofs = regofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) unit->bit = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) unit->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) unit->idle_bit = idle_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) unit->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) clk = clk_register(dev, &unit->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) kfree(unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static struct atlas7_reset_desc atlas7_reset_unit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock }, /* 0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock }, /* 6-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock }, /* 11-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock }, /* 16-20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock }, /* 21-25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock }, /* 26-30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock }, /* 31-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock }, /* 36-40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock }, /* 41-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock }, /* 46-50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock }, /* 51-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock }, /* 56-60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock }, /* 61-65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock }, /* 66-70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock }, /* 71-75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock }, /* 76- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int atlas7_reset_module(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) unsigned long reset_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * HW suggest unit reset sequence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * assert sw reset (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * setting sw clk_en to if the clock was disabled before reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * delay 16 clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * disable clock (sw clk_en = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * de-assert reset (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * after this sequence, restore clock or not is decided by SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) spin_lock_irqsave(reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* clock enable or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* restore clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) spin_unlock_irqrestore(reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static const struct reset_control_ops atlas7_rst_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .reset = atlas7_reset_module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static struct reset_controller_dev atlas7_rst_ctlr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .ops = &atlas7_rst_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .of_reset_n_cells = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static void __init atlas7_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct atlas7_div_init_data *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct atlas7_mux_init_data *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct atlas7_unit_init_data *unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sirfsoc_clk_vbase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (!sirfsoc_clk_vbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) panic("unable to map clkc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) clk = clk_register(NULL, &clk_cpupll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) clk = clk_register(NULL, &clk_mempll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) clk = clk_register(NULL, &clk_sys0pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) clk = clk_register(NULL, &clk_sys1pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) clk = clk_register(NULL, &clk_sys2pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) clk = clk_register(NULL, &clk_sys3pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) pll_div_table, &cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pll_div_table, &cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) pll_div_table, &cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pll_div_table, &mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) pll_div_table, &mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) pll_div_table, &mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pll_div_table, &sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) pll_div_table, &sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) pll_div_table, &sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pll_div_table, &sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) pll_div_table, &sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pll_div_table, &sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) pll_div_table, &sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) pll_div_table, &sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) pll_div_table, &sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pll_div_table, &sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pll_div_table, &sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pll_div_table, &sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) CLK_SET_RATE_PARENT, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) 12, 0, &cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) 13, 0, &cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) 14, 0, &cpupll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) 12, 0, &mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) 13, 0, &mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) 14, 0, &mempll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) 12, 0, &sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) 13, 0, &sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) 14, 0, &sys0pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) 12, 0, &sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) 13, 0, &sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) 14, 0, &sys1pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) 12, 0, &sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) 13, 0, &sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) 14, 0, &sys2pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) 12, 0, &sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) 13, 0, &sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) 14, 0, &sys3pll_ctrl1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) clk = clk_register(NULL, &clk_audio_dto.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) clk = clk_register(NULL, &clk_disp0_dto.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) clk = clk_register(NULL, &clk_disp1_dto.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) for (i = 0; i < ARRAY_SIZE(divider_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) div = ÷r_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) clk = clk_register_divider(NULL, div->div_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) div->shift, div->width, 0, div->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) clk = clk_register_gate(NULL, div->gate_name, div->div_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) div->gate_flags, sirfsoc_clk_vbase + div->gate_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) div->gate_bit, 0, div->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* ignore selector status register check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) mux = &mux_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) mux->parent_num, mux->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) sirfsoc_clk_vbase + mux->mux_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) mux->shift, mux->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) mux->mux_flags, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) BUG_ON(!clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) for (i = 0; i < ARRAY_SIZE(unit_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) unit = &unit_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) unit->flags, unit->regofs, unit->bit, unit->type, unit->idle_bit, unit->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) BUG_ON(!atlas7_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) clk_data.clks = atlas7_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) BUG_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) atlas7_rst_ctlr.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) reset_controller_register(&atlas7_rst_ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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