Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #define SIRFSOC_CLKC_CLK_EN0    0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define SIRFSOC_CLKC_CLK_EN1    0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define SIRFSOC_CLKC_REF_CFG    0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define SIRFSOC_CLKC_CPU_CFG    0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define SIRFSOC_CLKC_MEM_CFG    0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define SIRFSOC_CLKC_MEMDIV_CFG 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define SIRFSOC_CLKC_SYS_CFG    0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SIRFSOC_CLKC_IO_CFG     0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SIRFSOC_CLKC_DSP_CFG    0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SIRFSOC_CLKC_GFX_CFG    0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SIRFSOC_CLKC_MM_CFG     0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SIRFSOC_CLKC_GFX2D_CFG  0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SIRFSOC_CLKC_LCD_CFG    0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SIRFSOC_CLKC_MMC01_CFG  0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SIRFSOC_CLKC_MMC23_CFG  0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SIRFSOC_CLKC_MMC45_CFG  0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIRFSOC_CLKC_NAND_CFG	0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIRFSOC_CLKC_NANDDIV_CFG	0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIRFSOC_CLKC_PLL1_CFG0  0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_CLKC_PLL2_CFG0  0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIRFSOC_CLKC_PLL3_CFG0  0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIRFSOC_CLKC_PLL1_CFG1  0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIRFSOC_CLKC_PLL2_CFG1  0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIRFSOC_CLKC_PLL3_CFG1  0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIRFSOC_CLKC_PLL1_CFG2  0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_CLKC_PLL2_CFG2  0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIRFSOC_CLKC_PLL3_CFG2  0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIRFSOC_USBPHY_PLL_CTRL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)