^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on clock drivers for S3C64xx and Exynos4 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/s5pv210.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* S5PC110/S5PV210 clock controller register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPLL_LOCK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EPLL_LOCK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VPLL_LOCK 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define APLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPLL_CON 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EPLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EPLL_CON1 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VPLL_CON 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_SRC0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_SRC1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_SRC2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_SRC3 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_SRC4 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_SRC5 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_SRC6 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_SRC_MASK0 0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_SRC_MASK1 0x0284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_DIV0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_DIV1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_DIV2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_DIV3 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_DIV4 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_DIV5 0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_DIV6 0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_DIV7 0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_GATE_MAIN0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_GATE_MAIN1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_GATE_MAIN2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_GATE_PERI0 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_GATE_PERI1 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_GATE_SCLK0 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_GATE_SCLK1 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_GATE_IP0 0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_GATE_IP1 0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_GATE_IP2 0x0468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_GATE_IP3 0x046c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_GATE_IP4 0x0470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_GATE_BLOCK 0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_GATE_IP5 0x0484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_OUT 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MISC 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OM_STAT 0xe100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* IDs of PLLs available on S5PV210/S5P6442 SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) apll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) epll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) vpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* IDs of external clocks (used for legacy boards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) xxti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) xusbxti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* List of registers that need to be preserved across suspend/resume. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static unsigned long s5pv210_clk_regs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CLK_SRC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_SRC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CLK_SRC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_SRC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) CLK_SRC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_SRC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CLK_SRC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_SRC_MASK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CLK_SRC_MASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_DIV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CLK_DIV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CLK_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CLK_DIV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CLK_DIV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CLK_DIV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_DIV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CLK_GATE_MAIN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CLK_GATE_MAIN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_GATE_MAIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CLK_GATE_PERI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLK_GATE_PERI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CLK_GATE_SCLK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_GATE_SCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CLK_GATE_IP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLK_GATE_IP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CLK_GATE_IP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_GATE_IP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CLK_GATE_IP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_GATE_IP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CLK_GATE_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) APLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) VPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) APLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) APLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MPLL_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) VPLL_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CLK_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Mux parent lists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const char *const fin_pll_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "xxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "xusbxti"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char *const mout_apll_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "fout_apll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const char *const mout_mpll_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "fout_mpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char *const mout_epll_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "fout_epll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char *const mout_vpllsrc_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "sclk_hdmi27m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const char *const mout_vpll_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "mout_vpllsrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "fout_vpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const char *const mout_group1_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "dout_a2m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "mout_vpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const char *const mout_group2_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "xxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "sclk_hdmi27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "sclk_usbphy1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char *const mout_audio0_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "xxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "pcmcdclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "sclk_hdmi27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "sclk_usbphy1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const char *const mout_audio1_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "i2scdclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "pcmcdclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "sclk_hdmi27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "sclk_usbphy1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char *const mout_audio2_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "i2scdclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "pcmcdclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "sclk_hdmi27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "sclk_usbphy1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const char *const mout_spdif_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "dout_audio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "dout_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "dout_audio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char *const mout_group3_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "mout_apll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "mout_mpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char *const mout_group4_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "dout_a2m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const char *const mout_flash_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "dout_hclkd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "dout_hclkp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char *const mout_dac_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "sclk_hdmiphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char *const mout_hdmi_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "dout_tblk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const char *const mout_mixer_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "mout_dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "mout_hdmi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const char *const mout_vpll_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "fout_vpll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char *const mout_mixer_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "dout_mixer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char *const mout_d0sync_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "mout_dsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "div_apll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char *const mout_d1sync_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "mout_psys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "div_apll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char *const mout_group2_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char *const mout_audio0_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "pcmcdclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const char *const mout_audio1_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "i2scdclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "pcmcdclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "mout_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "mout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char *const mout_clksel_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "fout_apll_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "fout_mpll_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "fout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "fout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "sclk_usbphy1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "rtc_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "dout_hclkm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "dout_pclkm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "dout_hclkd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "dout_pclkd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "dout_hclkp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "dout_pclkp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "dout_apll_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "dout_hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "xxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "div_dclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const char *const mout_clksel_6442_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "fout_apll_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "fout_mpll_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "fout_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "fout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "rtc_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "dout_hclkd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "dout_pclkd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "dout_hclkp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "dout_pclkp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "dout_apll_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "div_dclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const char *const mout_clkout_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "dout_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "xxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "xusbxti"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Common fixed factor clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct samsung_mux_clock early_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) CLK_MUX_READ_ONLY, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Common clock muxes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct samsung_mux_clock mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* S5PV210-specific clock muxes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* S5P6442-specific clock muxes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* S5PV210-specific fixed rate clocks generated inside the SoC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* S5P6442-specific fixed rate clocks generated inside the SoC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Common clock dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct samsung_div_clock div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* S5PV210-specific clock dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* S5P6442-specific clock dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Common clock gates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct samsung_gate_clock gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* S5PV210-specific clock gates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) CLK_GATE_IP3, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* S5P6442-specific clock gates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Clock aliases for legacy clkdev look-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * NOTE: Needed only to support legacy board files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ALIAS(DOUT_APLL, NULL, "armclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* S5PV210-specific PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) APLL_LOCK, APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MPLL_LOCK, MPLL_CON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) EPLL_LOCK, EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) VPLL_LOCK, VPLL_CON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* S5P6442-specific PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) APLL_LOCK, APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MPLL_LOCK, MPLL_CON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) EPLL_LOCK, EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) VPLL_LOCK, VPLL_CON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static void __init __s5pv210_clk_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unsigned long xxti_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) unsigned long xusbxti_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) bool is_s5p6442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ctx = samsung_clk_init(np, reg_base, NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) samsung_clk_register_mux(ctx, early_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ARRAY_SIZE(early_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (is_s5p6442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ARRAY_SIZE(s5p6442_frate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) samsung_clk_register_pll(ctx, s5p6442_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ARRAY_SIZE(s5p6442_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) samsung_clk_register_mux(ctx, s5p6442_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ARRAY_SIZE(s5p6442_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) samsung_clk_register_div(ctx, s5p6442_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ARRAY_SIZE(s5p6442_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) samsung_clk_register_gate(ctx, s5p6442_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ARRAY_SIZE(s5p6442_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ARRAY_SIZE(s5pv210_frate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) samsung_clk_register_pll(ctx, s5pv210_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ARRAY_SIZE(s5pv210_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) samsung_clk_register_mux(ctx, s5pv210_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ARRAY_SIZE(s5pv210_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) samsung_clk_register_div(ctx, s5pv210_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ARRAY_SIZE(s5pv210_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) samsung_clk_register_gate(ctx, s5pv210_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ARRAY_SIZE(s5pv210_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) samsung_clk_register_fixed_factor(ctx, ffactor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ARRAY_SIZE(ffactor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) samsung_clk_register_alias(ctx, s5pv210_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ARRAY_SIZE(s5pv210_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) samsung_clk_sleep_init(reg_base, s5pv210_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ARRAY_SIZE(s5pv210_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "\tmout_epll = %ld, mout_vpll = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) is_s5p6442 ? "S5P6442" : "S5PV210",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) _get_rate("mout_apll"), _get_rate("mout_mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) _get_rate("mout_epll"), _get_rate("mout_vpll"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void __init s5pv210_clk_dt_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) __s5pv210_clk_init(np, 0, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void __init s5p6442_clk_dt_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __s5pv210_clk_init(np, 0, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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