^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on Exynos Audio Subsystem Clock Controller driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Padmavathi Venna <padma.v@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <dt-bindings/clock/s5pv210-audss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static DEFINE_SPINLOCK(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ASS_CLK_SRC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ASS_CLK_DIV 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ASS_CLK_GATE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned long reg_save[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {ASS_CLK_SRC, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {ASS_CLK_DIV, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {ASS_CLK_GATE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int s5pv210_audss_clk_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (i = 0; i < ARRAY_SIZE(reg_save); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) reg_save[i][1] = readl(reg_base + reg_save[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void s5pv210_audss_clk_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) for (i = 0; i < ARRAY_SIZE(reg_save); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) writel(reg_save[i][1], reg_base + reg_save[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct syscore_ops s5pv210_audss_clk_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .suspend = s5pv210_audss_clk_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .resume = s5pv210_audss_clk_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* register s5pv210_audss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int s5pv210_audss_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const char *mout_audss_p[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const char *mout_i2s_p[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const char *hclk_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_hw **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (IS_ERR(reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_err(&pdev->dev, "failed to map audss registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_data = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct_size(clk_data, hws, AUDSS_MAX_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk_data->num = AUDSS_MAX_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_table = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) hclk = devm_clk_get(&pdev->dev, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (IS_ERR(hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_err(&pdev->dev, "failed to get hclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return PTR_ERR(hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pll_in = devm_clk_get(&pdev->dev, "fout_epll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ERR(pll_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(&pdev->dev, "failed to get fout_epll clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return PTR_ERR(pll_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ERR(sclk_audio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return PTR_ERR(sclk_audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* iiscdclk0 is an optional external I2S codec clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pll_ref = devm_clk_get(&pdev->dev, "xxti");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!IS_ERR(pll_ref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mout_audss_p[0] = __clk_get_name(pll_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mout_audss_p[0] = "xxti";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mout_audss_p[1] = __clk_get_name(pll_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mout_audss_p, ARRAY_SIZE(mout_audss_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mout_i2s_p[0] = "mout_audss";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!IS_ERR(cdclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mout_i2s_p[1] = __clk_get_name(cdclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mout_i2s_p[1] = "iiscdclk0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mout_i2s_p[2] = __clk_get_name(sclk_audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "dout_aud_bus", "mout_audss", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "dout_i2s_audss", "mout_i2s_audss", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "dout_i2s_audss", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg_base + ASS_CLK_GATE, 6, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) hclk_p = __clk_get_name(hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hclk_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg_base + ASS_CLK_GATE, 5, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) hclk_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg_base + ASS_CLK_GATE, 4, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) hclk_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg_base + ASS_CLK_GATE, 3, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) hclk_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reg_base + ASS_CLK_GATE, 2, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) hclk_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) reg_base + ASS_CLK_GATE, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hclk_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg_base + ASS_CLK_GATE, 0, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < clk_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (IS_ERR(clk_table[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(&pdev->dev, "failed to register clock %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = PTR_ERR(clk_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(&pdev->dev, "failed to add clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) register_syscore_ops(&s5pv210_audss_clk_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < clk_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!IS_ERR(clk_table[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clk_hw_unregister(clk_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id s5pv210_audss_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "samsung,s5pv210-audss-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct platform_driver s5pv210_audss_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "s5pv210-audss-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .of_match_table = s5pv210_audss_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .probe = s5pv210_audss_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int __init s5pv210_audss_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return platform_driver_register(&s5pv210_audss_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) core_initcall(s5pv210_audss_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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