^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Common Clock Framework support for all S3C64xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk/samsung.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* S3C64xx clock controller register offsets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define APLL_LOCK 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPLL_LOCK 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EPLL_LOCK 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APLL_CON 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPLL_CON 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EPLL_CON0 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EPLL_CON1 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_SRC 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_DIV0 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_DIV1 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_DIV2 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HCLK_GATE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCLK_GATE 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCLK_GATE 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MEM0_GATE 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_SRC2 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OTHERS 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Helper macros to define clock arrays. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FIXED_RATE_CLOCKS(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct samsung_fixed_rate_clock name[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_CLOCKS(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct samsung_mux_clock name[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DIV_CLOCKS(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct samsung_div_clock name[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GATE_CLOCKS(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct samsung_gate_clock name[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Helper macros for gate types present on S3C64xx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GATE_BUS(_id, cname, pname, o, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE(_id, cname, pname, o, b, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GATE_SCLK(_id, cname, pname, o, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GATE_ON(_id, cname, pname, o, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static bool is_s3c6400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * List of controller registers to be saved and restored during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * a suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned long s3c64xx_clk_regs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) APLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) APLL_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MPLL_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) EPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CLK_DIV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_DIV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CLK_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HCLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PCLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SCLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static unsigned long s3c6410_clk_regs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CLK_SRC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MEM0_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* List of parent clocks common for all S3C64xx SoCs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PNAME(uart_p) = { "mout_epll", "dout_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "pcmcdclk0", "none", "none", "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "pcmcdclk0", "none", "none", "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PNAME(mfc_p) = { "hclkx2", "mout_epll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PNAME(apll_p) = { "fin_pll", "fout_apll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PNAME(epll_p) = { "fin_pll", "fout_epll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* S3C6400-specific parent clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* S3C6410-specific parent clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "pcmcdclk1", "none", "none", "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Fixed rate clocks generated outside the SoC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FRATE(0, "fin_pll", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FRATE(0, "xusbxti", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Fixed rate clocks generated inside the SoC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FRATE(CLK27M, "clk27m", NULL, 0, 27000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FRATE(CLK48M, "clk48m", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* List of clock muxes present on all S3C64xx SoCs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* List of clock muxes present on S3C6400. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* List of clock muxes present on S3C6410. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* List of clock dividers present on all S3C64xx SoCs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* List of clock dividers present on S3C6400. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DIV_CLOCKS(s3c6400_div_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* List of clock dividers present on S3C6410. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DIV_CLOCKS(s3c6410_div_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* List of clock gates present on all S3C64xx SoCs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* List of clock gates present on S3C6400. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* List of clock gates present on S3C6410. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* List of PLL clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) APLL_LOCK, APLL_CON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MPLL_LOCK, MPLL_CON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EPLL_LOCK, EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Aliases for common s3c64xx clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ALIAS(FOUT_APLL, NULL, "fout_apll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ALIAS(FOUT_EPLL, NULL, "fout_epll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ALIAS(MOUT_EPLL, NULL, "mout_epll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ALIAS(HCLKX2, NULL, "hclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ALIAS(HCLK, NULL, "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ALIAS(PCLK, NULL, "pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ALIAS(PCLK, NULL, "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ALIAS(ARMCLK, NULL, "armclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ALIAS(PCLK_PWM, NULL, "timers"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ALIAS(PCLK_WDT, NULL, "watchdog"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ALIAS(SCLK_CAM, "s3c-camif", "camera"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Aliases for s3c6400-specific clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct samsung_clock_alias s3c6400_clock_aliases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Nothing to place here yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Aliases for s3c6410-specific clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct samsung_clock_alias s3c6410_clock_aliases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ALIAS(MEM0_SROM, NULL, "srom"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void __init s3c64xx_clk_register_fixed_ext(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct samsung_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long fin_pll_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned long xusbxti_f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Register s3c64xx clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long xusbxti_f, bool s3c6400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) is_s3c6400 = s3c6400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ctx = samsung_clk_init(np, reg_base, NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Register external clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Register PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Register common internal clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ARRAY_SIZE(s3c64xx_fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ARRAY_SIZE(s3c64xx_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) samsung_clk_register_div(ctx, s3c64xx_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ARRAY_SIZE(s3c64xx_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ARRAY_SIZE(s3c64xx_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Register SoC-specific clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (is_s3c6400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) samsung_clk_register_mux(ctx, s3c6400_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ARRAY_SIZE(s3c6400_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) samsung_clk_register_div(ctx, s3c6400_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ARRAY_SIZE(s3c6400_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) samsung_clk_register_gate(ctx, s3c6400_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ARRAY_SIZE(s3c6400_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ARRAY_SIZE(s3c6400_clock_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) samsung_clk_register_mux(ctx, s3c6410_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ARRAY_SIZE(s3c6410_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) samsung_clk_register_div(ctx, s3c6410_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ARRAY_SIZE(s3c6410_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) samsung_clk_register_gate(ctx, s3c6410_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ARRAY_SIZE(s3c6410_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ARRAY_SIZE(s3c6410_clock_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ARRAY_SIZE(s3c64xx_clock_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ARRAY_SIZE(s3c64xx_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!is_s3c6400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) samsung_clk_sleep_init(reg_base, s3c6410_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ARRAY_SIZE(s3c6410_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pr_info("%s clocks: apll = %lu, mpll = %lu\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "\tepll = %lu, arm_clk = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) is_s3c6400 ? "S3C6400" : "S3C6410",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) _get_rate("fout_apll"), _get_rate("fout_mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) _get_rate("fout_epll"), _get_rate("armclk"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void __init s3c6400_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) s3c64xx_clk_init(np, 0, 0, true, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void __init s3c6410_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) s3c64xx_clk_init(np, 0, 0, false, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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