^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Common Clock Framework support for S3C2443 and following SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/samsung.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/s3c2443.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* S3C2416 clock controller register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LOCKCON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LOCKCON1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPLLCON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EPLLCON 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EPLLCON_K 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLKSRC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLKDIV0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLKDIV1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLKDIV2 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HCLKCON 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCLKCON 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCLKCON 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SWRST 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* the soc types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum supported_socs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) S3C2416,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) S3C2443,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) S3C2450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * list of controller registers to be saved and restored during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static unsigned long s3c2443_clk_regs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) LOCKCON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) LOCKCON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MPLLCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EPLLCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EPLLCON_K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CLKSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CLKDIV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CLKDIV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLKDIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PCLKCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) HCLKCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SCLKCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PNAME(esysclk_p) = { "epllref", "epll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PNAME(mpllref_p) = { "xti", "mdivclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PNAME(msysclk_p) = { "mpllref", "mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PNAME(armclk_p) = { "armdiv" , "hclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct clk_div_table hclk_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clk_div_table mdivclk_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .val = 1, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .val = 2, .div = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .val = 3, .div = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .val = 4, .div = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .val = 5, .div = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .val = 6, .div = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .val = 7, .div = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ALIAS(MSYSCLK, NULL, "msysclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ALIAS(ARMCLK, NULL, "armclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ALIAS(MPLL, NULL, "mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ALIAS(EPLL, NULL, "epll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ALIAS(HCLK, NULL, "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ALIAS(HCLK_SSMC, NULL, "nand"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ALIAS(PCLK_PWM, NULL, "timers"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ALIAS(PCLK_RTC, NULL, "rtc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ALIAS(PCLK_WDT, NULL, "watchdog"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ALIAS(PCLK_ADC, NULL, "adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ALIAS(HCLK_USBD, NULL, "usb-device"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ALIAS(HCLK_USBH, NULL, "usb-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ALIAS(SCLK_I2S0, NULL, "i2s-if"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ALIAS(HCLK_LCD, NULL, "lcd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* S3C2416 specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct clk_div_table armdiv_s3c2416_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .val = 5, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .val = 7, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct samsung_div_clock s3c2416_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct samsung_mux_clock s3c2416_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct samsung_gate_clock s3c2416_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct samsung_clock_alias s3c2416_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ALIAS(ARMDIV, NULL, "armdiv"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* S3C2443 specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct clk_div_table armdiv_s3c2443_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .val = 8, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .val = 9, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .val = 10, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .val = 11, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { .val = 13, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { .val = 15, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct samsung_div_clock s3c2443_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct samsung_gate_clock s3c2443_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct samsung_clock_alias s3c2443_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ALIAS(SCLK_CAM, NULL, "camif-upll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ALIAS(PCLK_SDI, NULL, "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ALIAS(HCLK_CFC, NULL, "cfc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ALIAS(ARMDIV, NULL, "armdiv"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* S3C2450 specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct samsung_div_clock s3c2450_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct samsung_mux_clock s3c2450_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct samsung_gate_clock s3c2450_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct samsung_clock_alias s3c2450_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int s3c2443_restart(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long mode, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __raw_writel(0x533c2443, reg_base + SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct notifier_block s3c2443_restart_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .notifier_call = s3c2443_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .priority = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * fixed rate clocks generated outside the soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Only necessary until the devicetree-move is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FRATE(0, "xti", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FRATE(0, "ext", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FRATE(0, "ext_i2s", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FRATE(0, "ext_uart", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void __init s3c2443_common_clk_register_fixed_ext(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct samsung_clk_provider *ctx, unsigned long xti_f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) s3c2443_common_frate_clks[0].fixed_rate = xti_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ARRAY_SIZE(s3c2443_common_frate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int current_soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ctx = samsung_clk_init(np, reg_base, NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Register external clocks only in non-dt cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Register PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (current_soc == S3C2416 || current_soc == S3C2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) samsung_clk_register_pll(ctx, s3c2416_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ARRAY_SIZE(s3c2416_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) samsung_clk_register_pll(ctx, s3c2443_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ARRAY_SIZE(s3c2443_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Register common internal clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) samsung_clk_register_mux(ctx, s3c2443_common_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ARRAY_SIZE(s3c2443_common_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) samsung_clk_register_div(ctx, s3c2443_common_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ARRAY_SIZE(s3c2443_common_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) samsung_clk_register_gate(ctx, s3c2443_common_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ARRAY_SIZE(s3c2443_common_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) samsung_clk_register_alias(ctx, s3c2443_common_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ARRAY_SIZE(s3c2443_common_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Register SoC-specific clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (current_soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case S3C2450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) samsung_clk_register_div(ctx, s3c2450_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ARRAY_SIZE(s3c2450_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) samsung_clk_register_mux(ctx, s3c2450_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ARRAY_SIZE(s3c2450_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) samsung_clk_register_gate(ctx, s3c2450_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ARRAY_SIZE(s3c2450_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) samsung_clk_register_alias(ctx, s3c2450_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ARRAY_SIZE(s3c2450_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fallthrough; /* as s3c2450 extends the s3c2416 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case S3C2416:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) samsung_clk_register_div(ctx, s3c2416_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ARRAY_SIZE(s3c2416_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) samsung_clk_register_mux(ctx, s3c2416_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ARRAY_SIZE(s3c2416_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) samsung_clk_register_gate(ctx, s3c2416_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ARRAY_SIZE(s3c2416_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) samsung_clk_register_alias(ctx, s3c2416_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ARRAY_SIZE(s3c2416_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case S3C2443:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) samsung_clk_register_div(ctx, s3c2443_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ARRAY_SIZE(s3c2443_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) samsung_clk_register_gate(ctx, s3c2443_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ARRAY_SIZE(s3c2443_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) samsung_clk_register_alias(ctx, s3c2443_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ARRAY_SIZE(s3c2443_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ARRAY_SIZE(s3c2443_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = register_restart_handler(&s3c2443_restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pr_warn("cannot register restart handler, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void __init s3c2416_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) s3c2443_common_clk_init(np, 0, S3C2416, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void __init s3c2443_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) s3c2443_common_clk_init(np, 0, S3C2443, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void __init s3c2450_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) s3c2443_common_clk_init(np, 0, S3C2450, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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