Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Common Clock Framework support for S3C2412 and S3C2413.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk/samsung.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/clock/s3c2412.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LOCKTIME	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MPLLCON		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UPLLCON		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLKCON		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLKDIVN		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLKSRC		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SWRST		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * list of controller registers to be saved and restored during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static unsigned long s3c2412_clk_regs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	LOCKTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	MPLLCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	UPLLCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	CLKCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	CLKDIVN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	CLKSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct clk_div_table divxti_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ .val = 3, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ .val = 4, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ .val = 5, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ .val = 6, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ .val = 7, .div = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct samsung_div_clock s3c2412_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * The first two use the OM[4] setting, which is not readable from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * software, so assume it is set to xti.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) PNAME(camclk_p) = { "usysclk", "hclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) PNAME(usbclk_p) = { "usysclk", "hclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) PNAME(i2sclk_p) = { "erefclk", "mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) PNAME(uartclk_p) = { "erefclk", "mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) PNAME(usysclk_p) = { "urefclk", "upll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) PNAME(msysclk_p) = { "mdivclk", "mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) PNAME(mdivclk_p) = { "xti", "div_xti" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) PNAME(armclk_p) = { "armdiv", "hclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static struct samsung_mux_clock s3c2412_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct samsung_pll_clock s3c2412_plls[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct samsung_gate_clock s3c2412_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct samsung_clock_alias s3c2412_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ALIAS(PCLK_ADC, NULL, "adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ALIAS(PCLK_RTC, NULL, "rtc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ALIAS(PCLK_PWM, NULL, "timers"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ALIAS(HCLK_LCD, NULL, "lcd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ALIAS(PCLK_USBD, NULL, "usb-device"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ALIAS(HCLK_USBH, NULL, "usb-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ALIAS(ARMCLK, NULL, "armclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ALIAS(HCLK, NULL, "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ALIAS(MPLL, NULL, "mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ALIAS(MSYSCLK, NULL, "fclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int s3c2412_restart(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   unsigned long mode, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* errata "Watch-dog/Software Reset Problem" specifies that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * this reset must be done with the SYSCLK sourced from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * EXTCLK instead of FOUT to avoid a glitch in the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * See the watchdog section of the S3C2412 manual for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 * information on this fix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	__raw_writel(0x00, reg_base + CLKSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	__raw_writel(0x533C2412, reg_base + SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct notifier_block s3c2412_restart_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.notifier_call = s3c2412_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.priority = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * fixed rate clocks generated outside the soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * Only necessary until the devicetree-move is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define XTI	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	FRATE(XTI, "xti", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	FRATE(0, "ext", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void __init s3c2412_common_clk_register_fixed_ext(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		struct samsung_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		unsigned long xti_f, unsigned long ext_f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* xtal alias is necessary for the current cpufreq driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	s3c2412_common_frate_clks[0].fixed_rate = xti_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	s3c2412_common_frate_clks[1].fixed_rate = ext_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				ARRAY_SIZE(s3c2412_common_frate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	samsung_clk_register_alias(ctx, &xti_alias, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				    unsigned long ext_f, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ctx = samsung_clk_init(np, reg_base, NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Register external clocks only in non-dt cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Register PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				 reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Register common internal clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	samsung_clk_register_div(ctx, s3c2412_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					  ARRAY_SIZE(s3c2412_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	samsung_clk_register_gate(ctx, s3c2412_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					ARRAY_SIZE(s3c2412_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					  ARRAY_SIZE(s3c2412_ffactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	samsung_clk_register_alias(ctx, s3c2412_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				   ARRAY_SIZE(s3c2412_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			       ARRAY_SIZE(s3c2412_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = register_restart_handler(&s3c2412_restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pr_warn("cannot register restart handler, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void __init s3c2412_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	s3c2412_common_clk_init(np, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);